Re: need time delay 555 / 556 circuit help

From: John Fields (jfields_at_austininstruments.com)
Date: 06/24/04 

Date: Thu, 24 Jun 2004 11:10:34 -0500

On 23 Jun 2004 21:16:18 -0700, rpaisley4@cogeco.ca (Rob Paisley)
wrote:

>John Fields <jfields@austininstruments.com> wrote in message news:<00fjd0litv9v0obd64fd599f9ptr95k5s1@4ax.com>...
>> On 23 Jun 2004 09:44:31 -0700, fiddlerxl@hotmail.com (Fiddler) wrote:
>>
>> >I need a very simple circuit. When it's on, I need it to stay off for
>> >a few seconds, then output a pulse for a few seconds then turn off.
>> >This theoretically could be done with a 556 with both halves working
>> >as monostable oneshot timers. However, when I tried this i had some
>> >weird results. First off, I need this to be triggered when power is
>> >applied to the circuit, not when the trigger pin is activated so I
>> >just tied it to ground.
>> >what happens afterwards is a bit weird. At first, both outputs go
>> >high (from both halves) then the first one times out and triggers the
>> >second one. However, I dont need that initial spike since this needs
>> >to latch a relay after a few seconds wait. The other problem is that
>> >the timing capacitor on the second half of the circuit seems to affect
>> >the delays on both halves.
>> >the one thing so far that i havent checked into is power supply i'm
>> >using. So far I've been testing this w/ a 9v battery (i dont know how
>> >fresh it is).. if the battery is weak, can it cause this kind of an
>> >issue?
>> >
>> >My circuit is wired like this:
>> >http://home.cogeco.ca/~rpaisley4/LM555Delays2.GIF
>> >except for the first trigger which is tied to ground.
>> >Is there a way to prevent that initial trigerring of the second part
>> >of the circuit.. or rather keep it intentionally low until the first
>> >half triggers it?
>>
>> ---
>> Yes.
>>
>> With 556s or 7556s:
>>
>> VCC>--+---------+-------+----------+-------+-------+
>> | | | | | |
>> [10K] +---+---+ [1M] [10K] +---+---+ [1M]
>> | |__ | | | |__ | |
>> +----O|TR OUT|-----[100nF]--+--O|TR OUT|------->OUT
>> | | _| | | _| |
>> | | D|O--+ | D|O--+
>> | |_ | | |_ | |
>> | +-O|R TH|---+ +-O|R TH|---+
>> | | +-------+ |+ | +-------+ |+
>> [10nF]| 1/2 7556 [3.3µF] | 1/2 7556 [3.3µF]
>> | | | | |
>> GND>--+--+--------------+-----------+--------------+--->GND
>>
>
>
> The RESET terminals in the above circuit need to be tied to the
>positive. 

---
No, but I did make a mistake.  Thanks for waking me up.  Here's how
they _should_ be connected:
 VCC>--+---------+-------+----------+-------+-------+
       |         |       |          |       |       | 
     [10K]   +---+---+  [1M]      [10K] +---+---+ [1M]
       |     |__     |   |          |   |__     |   |
       +----O|TR OUT1|-----[100nF]--+--O|TR OUT2|------->OUT
       |     |      _|   |              |      _|   |
       |     |      D|O--+              |      D|O--+
       |     |_      |   |              |_      |   |
       +--+-O|R    TH|---+           +-O|R    TH|---+
       |  |  +-------+   |+          |  +-------+   |+
    [10nF]|  1/2 7556  [3.3µF]       |  1/2 7556  [3.3µF] 
       |  |              |           |              |
       |  +--------------------------+              |
       |                 |                          |
 GND>--+-----------------+--------------------------+--->GND
Notice that this connection will prevent triggering of the second
timer on power-up, but will allow the first timer to trigger on as
soon as  the reset voltage to > 1.2V. (regardless of Vcc, BTW)  When
the reset voltage rises above 1.2V the trigger input will still be
low, so that  will force the output of the first timer to go high and
start timing out because its trigger input will still be active since
the 10nF cap won't yet have charged up to > 1/3 Vcc and won't go
inactive until it gets to 1/3 Vcc.  When it does go inactive, the
output will still be timing out, which satisfies the criterion that
the input pulse be narrower than the output pulse.
Now, since the output of the first timer will be high when the reset
input to both timers goes high, _and_ since the second timer's trigger
input will be pulled up to Vcc, it will be impossible for the second
timer to be triggered at that time.  However, when the first timer
times out and its output goes low, that low-going edge will be
differentiated by the 100nF cap, the second timer's trigger input will
be pulled low momentarily and the second timer's output will go high
for the period determined by the 1 megohm resistor and the 3.3µF
capacitor; about 3.6 seconds.  Since the period of the first timer is
also about 3.6s, that should come close to the OP's request for no
output for 3 seconds after power-up, followed by 3 seconds of output,
followed by no output thereafter.  If it doesn't work for him he can
easily change the caps or the resistors to get what he wants, since 
T = 1.1RC
Here's the timing:
          ______________________________________________
PWRON____|   
           _____________________________________________
RESET_____|     
            __________
OUT1_______|          |_________________________________
                        __________
OUT2___________________|          |_____________________
---
>  Adding the following circuit to the second timer should prevent it
>from triggering when the power is applied.
>
>http://home.cogeco.ca/~rpaisley4/LM555.html#10
---
Thanks, but the fix shown above should work fine.  BTW, I noticed that
in almost all of the circuits you have you've allowed the reset input
to float.  That's probably not as good as tying it to the positive
supply would be, as you noted above.  Noise and high impedance inputs
and all that...
---
>  A 9 volt battery is not a very good power supply for this circuit.
---
I can't imagine why not; got a reason or two?-)
-- 
John Fields

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