Re: common emitter configuration- voltage divider biasing.

From: Joe (nuisancewildlife_at_nospamearthlink.net)
Date: 07/31/04 

Date: Sat, 31 Jul 2004 20:16:31 GMT

"Jonathan Kirwan" <jkirwan@easystreet.com> wrote in message
news:99lng0tnhu70kngqnqfpiksc94f5abccuv@4ax.com...
> On Sat, 31 Jul 2004 02:53:25 GMT, "Joe"
<nuisancewildlife@nospamearthlink.net>
> wrote:
>
> >This is becoming an interesting discussion. From what I can understand,
the
> >emitter cap is there to shunt (if that's the right word) certain
frequencies
> >to ground so they don't get amplified.
>
> Like I said before, I don't really understand the use of the topology
shown at
> that site. Given what they drew there, of course, as the frequency
increases,
> the shunting gets more pronounced.
>
> But the problem as I see it in that example is that if the capacitor is
sized to
> effectively bypass the emitter R at some low frequency and for those
frequencies
> above that point (until other factors dominate and change what I'm about
to
> say), then the emitter is essentially grounded above that frequency point.
So,
> let's say you size it to bypass the emitter R at 100Hz and above, then for
those
> frequencies the Z of the capacitor will be diminishingly tiny and the
emitter
> will be, in effect, at ground.

Hi Jon,

Ok, so, judging from the other responses, I have been looking at things sort
of bass ackwards :-)

>
> This isn't a good thing, usually. What it means is that the gain is then
based
> on R(C)/(r(e)+Z(c-bypass)) and, since r(e) is highly dependent on I(C),
the gain
> will be varying all over the place. Similarly, if the Z of the capacitor
hasn't
> yet diminished to the point where it is very much smaller than r(e)
itself, then
> the frequency will also be varying the gain all over the place, too.
>
> It's not good.

I was thinking that the emitter cap would in most cases be shunting out
unwanted frequency. Say for audio, you want from 20hz to 20Khz but get rid
of anything above 20Khz, so you calculate your Ce for 20Khz. Now I can
understand a little better that the Ce is actually feeding back those
frequencies to get more gain. OK, again I was looking at it wrong. In this
case, you would choose the emitter resistor to pass all frequencies above
20hz to get your audio amplification.
>
> >But when you figure out the cap, you
> >have to use the lowest frequency you wish to eliminate (shunt?)
>
> You would use the lower frequency that you want to shunt, yes. But that
is the
> reverse way to look at it. You are actually setting the lower end of the
> __desirable__ frequency band. Frequencies less than this will get smaller
gains
> and will therefore diminish in their relative presence in the output
because
> they are NOT bypassed by the C.

OK, got it.

>
> Here's a better topology (not the only one, though):
>
> V+ V+
> | |
> | |
> | |
> \ \
> / Rb1 / Rc
> \ \
> | |
> | +--------> OUT
> | |
> | |
> | b|/c Q1
> +-------| NPN
> | |\e
> IN >-----+ v
> | |
> | +-------,
> | | |
> | | \
> | | / Rac
> | \ \
> \ / Re |
> / Rb2 \ |
> \ | |
> | | --- Cac
> | | ---
> | | |
> | | |
> --- --- ---
> gnd gnd gnd
>
>
> Without getting into more complex models, gain is:
>
> Rc / ( r(e) + ( Re || (Rac + Z(Cac)) ) )
>
> Here, you can see that Cac acts similarly, but that when its Z is tiny,
then the
> resulting gain is set by Rc/(r(e)+(Re||Rac)). (|| means the parallel
equivalent
> resistance.)

So do I read the above correctly? Cac is in series with Re? I am not too
good at reading ascii schematics.

>
> In other words, you design the DC operating point by ignoring Rac and Cac,
at
> first. Once the DC operating point is established in that way, then you
design
> Rac and Cac so that when the frequency rises above some given point, Cac
will be
> an effective bypass, tying Rac to ground. But NOT the emitter itself!

OK, understood, the problem I was having was with choosing the DC operating
point. I use mostly small signal transistors , but usually just as a switch.
I wanted a general set of equations that I could use for any common emitter
application.

>
> That way, you can design this to have a predictable gain that doesn't vary
much
> over I(C) or over frequency, once that low frequency is reached (and
beyond)
> because you can arrange things so that (Re||Rac) is still large compared
with
> r(e) "little r-e" and also that Rac is large compared to the Z of Cac at
and
> above some design frequency. Since (Re||Rac) also isn't dependent on the
> frequency at all because the Z of Cac is also diminishingly tiny by
comparison,
> the gain can be made relatively stable over a wide range of frequencies.

Probly the best thing for me to do is LTspice some of these circuits and
look at the output waveforms, and then possibly breadboard them and check
them on the scope. I have not built many common emitter amps so maybe I need
to do that.

>
> >and then
> >all frequencies higher than that also get eliminated. So is it sort of a
> >low pass filter?
>
> No, the other way around. Since frequencies lower than this set a high Z,
the
> gain of the amplifier at those still lower frequencies declines until the
Z is
> very much greater than the emitter resistor and that emitter resistor then
sets
> the low gain limit. Since higher frequencies have a higher gain (and in
that
> web site's design, a continually rising gain that doesn't make sense,
usually),
> they appear more dramatically in the output.
>
> >One other thing I noticed about using their equations is
> >that the emitter resistor is almost always 10% of the collector resistor.
>
> Well, in general, you usually want some gain! If the emitter resistor
were
> larger, you'd be attenuating the signals instead of increasing them.
Sometimes,
> that's what you want. But not here, I think.

My point was just why 10%? If it were 20 or 30 or 50%, there would still be
some gain. I am probly trying to generalize too much to make designs easier.

>
> >I
> >started using their method because I didn't know how to calculate the
bias
> >voltage divider for some transistors I couldn't find the curves for.
>
> I went through some of the calculation steps in detail, earlier. Did you
read
> them? Did they make any sense?

Yes, they made sense to me, but, as you can see, I was not thinking quite
right. :-(

Also, most small transistors (BJTs) can work
> just fine on a quiescent I(C) of anywhere from 0.4mA to 20mA, and probably
even
> wider than that. If you want to just play and aren't designing anything
in
> particular, I'd pick a quiescent I(C) of 1mA and build up a circuit on
that
> basis.

That is probly a good idea, as I mentioned above, there's no substitute for
experience.

>
> Like others have pointed out, a real design will need to account for what
is
> driving the circuit and what the circuit is supposed to drive, itself.
For
> example, if you are driving your 'test' amplifier circuit from an
oscillator or
> even a square wave generator, then how are you going to hook that up? Do
you
> imagine just tying one end to ground and the other end to the supposed
input at
> the BJT base? Through a resistor of some kind? Through a capacitor of
some
> value?

They show how to compute the value of the input cap, and output cap, but
don't really explain if a resistor is needed.

How? And some inputs, like say a microphone or some other kind of
> transducer, may have very particular requirements in order to operate
well.
>
> Usually, you have some kind of circuit designed to accommodate your
transducer
> and allow it to operate well. So that circuit is designed to meet the
need of
> the transducer and reflect the signal accurately into the next stage,
which
> often IS designed for some gain. But the first stage/circuit is more
designed
> for the transducer. Then you might have several stages of voltage
amplification
> after that. Finally, followed by yet another circuit designed for the
type of
> output transducer -- for example, such as a speaker. That last stage will
again
> be tailored for the output transducer and not for voltage gain, itself.
>
> In the above case example I gave, where the amplifier is designed for
voltage
> gain at some AC frequency and above, it might look more like:
>
>
> V+ V+
> | |
> | |
> | |
> \ \
> / Rb1 / Rc
> \ \
> | |
> | +--------> OUT
> | | (perhaps to another capacitor input)
> | |
> | b|/c Q1
> +-------| NPN
> || | |\e
> IN >----||---+ v
> || | |
> | +-------,
> Cin | | |
> | | \
> | | / Rac
> | \ \
> \ / Re |
> / Rb2 \ |
> \ | |
> | | --- Cac
> | | ---
> | | |
> | | |
> --- --- ---
> gnd gnd gnd
>
>
> Cin would be sized, like Cac, to pass frequencies above some point very
well.
> Using a capacitor there allows the DC biasing network to do it's job and
> correctly bias Q1 and to maintain that bias as higher frequency signals
are
> passed on by Cin. Any DC setpoint from the input side of Cin won't pull
down or
> pull up the DC biasing -- it will simply charge Cin and leave it charged.

I think I am getting lost now. I cannot read the above schematic, but I have
never seen a DC setpoint on the input side of an input cap. The cap would
block it wouldn't it? Then there would be no biasing on the transistor, it
may just act like a switch depending on what frequency is input to it.

>
> >Then I
> >started to incorporate all their equations into my spread*** so that
now I
> >can build one from input to output. They made it easy, all you need to
enter
> >is the hfe, Vcc, desired collector current and frequencies to pass.
>
> I've done similar things with LTSpice.
>
> Jon

I think I will be using LTSPICE more often (it is quicker than
breadboarding, but I figured it wouldn't always reflect the real world) and
trying different configurations using the equations and then just picking a
bias current as you stated earlier and see what the differences are.

Thanks for your patience explaining this to me. Thanks to everyone else who
replied. I am getting clearer on this now.

Joe