Re: PLL confusion

From: John Larkin (jjlarkin_at_highlandSNIPtechTHISnologyPLEASE.com)
Date: 11/14/04 

Date: Sun, 14 Nov 2004 11:38:01 -0800

On Sun, 14 Nov 2004 18:40:16 GMT, jim <road12fg@netscape.net> wrote:

>On Fri, 12 Nov 2004 16:32:11 -0800, John Larkin
><jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:
>
>>On Fri, 12 Nov 2004 21:12:26 GMT, jim <road12fg@netscape.net> wrote:
>>
>>>I'm trying to learn about PLL circuits and admittedly I'm a newbie and
>>>therefore confused as usual. Why is the phase detector portion of a
>>>phase lock loop (analog) called "phase detector" when what it really
>>>detects is a difference in frequency. That is two waveforms with
>>>different frequencies cannot have any fixed phase relationship.
>>
>>If the frequencies are different, the phase is "rolling."
>>
>>> As I
>>>understand it putting two identical frequencies that are some fixed
>>>phase apart will not give any signal out of the phase detector, only
>>>two different frequencies will give a dc current out.
>>
>>No, it detects and indicates phase. The result is some DC level if the
>>frequencies are truly equal, or a "rolling dc" level (which is
>>typically a sine or triangle wave) if they are really different.
>>
> I'm pretty visually oriented so my questions come from that angle,
>so I'm picturing the output of a pll of two signals that are
>identical in frequency which will be a flat dc level. Does the whole
>loop then try to bring the dc level to zero or is matching frequencies
>enough?
>

If there's just some DC gain from the pd output to the vco input
(maybe just g=1, even), the loop will usually settle with some
non-zero pd output, namely the voltage necessary to pull the vco to
the target frequency. Since it almost always takes some non-zero dc
voltage to pull the vco to the target, there must be a steady-state
phase error, so the waveforms are locked in frequency but have some
fixed phase offset, whatever it takes to tune the vco. This is a
first-order pll.

But if you add an integrator in the path from the phase detector
output to the vco input, the loop will settle at zero frequency error
and zero phase error (ignoring any residual offset errors in the pd or
the integrator.) The integrator will slowly creep the vco input over
time such as to servo the pd output to zero. This is a second-order
pll.

The vco-phase detector combination is itself mathematically an
integrator - just imagine applying a small DC voltage at the vco
input... the pd output will then be a ramp (although the ramp
eventually folds over, but that's another story... no integrator can
ramp forever!) So the type-1 servo loop is an integrator with negative
feedback, which is usually very stable. The type 2 loop has *two*
integrators in a feedback loop, which tends to be unstable,
oscillating or ringing badly (two integrators tend to chase each
others' tails, so to speak) so some additional compensation is needed
to keep the lock stable.

Beyond this, a good book on pll's would be helpful. Unfortunately,
many are mainly mathematical in approach, which is fine for coming to
workable solutions but somewhat lacking if you want an instinctive
visual feel for what's happening.

My favorite pll uses a d-type flipflop as the phase detector in a
type-1 loop. It's inherently stable, but has zero phase error, because
the phase detector gain is infinite. Mathematically, it's sort of a
mess.

>>Classic (simple) phase detectors detect phase difference, not
>>frequency difference. So if the two input frequencies are, say, 10 Hz
>>apart, the pd output is a sine or triangle wave at 10 Hz. If the
>>signals are the same frequency but differ in phase (timing) the pd
>>will give a corresponding DC out.
>>
>>Such a classic pd (a multiplier, diode mixer, xor gate, d-flipflop
>>etc) when fed into the oscillator control loop will result in lock
>>only if the phase change is relatively slow, which only happens if the
>>frequencies are close. If the frequencies are too far apart, the pd
>>output is a high-frequency waveform with no dc component that just
>>confuses the vco. So a simple pll has a limited "acquisition range",
>>even though it may track a wide range *once it gets into lock*.
>>
>>There are complex phase detectors that are smart enough to realize
>>that they are way out of lock, in which case they force the pd output
>>in the right direction until they're close enough to work in true
>>phase-detect mode. That solves the acquisition problem.
>
> I can picture the visual way to obtain phase difference of two
>different frequencies of equal amplitude by just drawing a horizontal
>line through the two waves at any amplitude and this will give the
>rolling phase difference. But what will be the effect on the phase
>detector output if one of the waves is say twice the amplitude.? If
>there is a difference how does the phase detector deal with this?
>

Some phase detectors (like a linear multiplier) give an output that
depends on one or both input amplitudes, so loop behavior varies with
input signal level (vco level is usually pretty much constant.) Most
pd's don't care about input amplitude for reasonable input levels, but
just compare phases; that simplifies loop analysis. An XOR gate is a
nice phase detector that pretty much ignores input level. Just imagine
turning either sine input into a square wave of, say, +-1 volt fixed
signal level, using a comparator or some such, and then comparing
phases.

John

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