Re: Learning to use PICS

From: Byron A Jeff (byron_at_cc.gatech.edu)
Date: 11/29/04 

Date: 29 Nov 2004 13:01:09 -0500

In article <364fd697.0411290907.7a86f50b@posting.google.com>,
David Harper <dave.harper@gmail.com> wrote:
>All,
>I appreciate everyone's suggestions and help so far. Right now I've
>started diving into understanding the architecture and memory of a
>typical PIC (16C84), which I figure is the best place to start. After
>that, I figure the programming will be a lot easier to understand.

The part you picked is ultra anchient. Might I suggest a 16F88.
I have a page on rationale here:

http://www.finitesite.com/d3jsys/16F88.html

>
>The program memory I understand, no problem (like the BS2, only it
>seems only instructions can be written at these locations for PICS,
>and only during programming).

Correct to a point. Chips like the 16F88 are self programmable, so they can
write their own program memory. This leads to the possibility of a bootloader
where there is no true programmer because the chip programs itself. Note that
you have to use a traditional programmer to get the bootloader onto the chip.

>
>However, with the data memory allocation, I'm having some difficulty
>based on some of the online datasheets:
>http://ww1.microchip.com/downloads/en/DeviceDoc/30445c.pdf
>
>and beginner guides (from piclist.com):
>http://www.piclist.com/techref/microchip/intro/pic.htm
>
>>From what I've read, there are 2 banks each divided into 128
>registers. The first 12 registers are SPR, which more or less define
>the chip's current state.

They give you access to periperals such as the timer and I/O ports. Later
chips have a bunch more.

> The next 32 registers are GPR (like RAM?).

RAM. An ultra limited amount too.

>What are the next 88? It's defined as "unimplemented data" according
>to Fig 4-2 in the 16C84 data***.

As specified. Nothing there. Unusable.

>
>Secondly, figure 4-7 (pg 18) shows 4 banks, not just two... just how
>many banks are there for this chip? Can it be more than 2 banks for
>different PICS, which is why they're showing it as 'off limits', so to
>speak?

Right.
>
>Lastly, back in figure 4-2, it states the 36 GPR in bank 1 are mapped
>to bank 0. Does this mean they're connected, and if a GPR in bank X
>changes, then the same GPR in the other bank will change also?

Yes.

> If so, are any of the SPR connected in this fashion?

Some. For example the STATUS register is usually mapped into every bank.

>
>Thanks for the patience if you've made it this far, and I really
>appreciate the help!

No problem.

But I beg of you not to get caught with the 16C84 or 16F84. They are older
than dirt. The newer chips bring a lot to the table, and cost less than the
older chips. Take a read of my page for more info.

BAJ

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