Re: Second Stage of Op-Am (Current to Voltage)

From: Larry Brasfield (donotspam_larry_brasfield_at_hotmail.com)
Date: 12/28/04 

Date: Tue, 28 Dec 2004 12:09:45 -0800

"Active8" <reply2group@ndbbm.net> wrote in message news:9d5t5ofpc4fj.dlg@news.individual.net...
> On Tue, 28 Dec 2004 05:12:04 -0800, Larry Brasfield wrote:
>
>> "Monty Hall" <chickenkungpao@hotmail.com> wrote in message news:_mbAd.3725$li1.1840@newssvr31.news.prodigy.com...
>>> From the schematic below, can Iout be bidirectional?
>>
>> Yes. Iout is the difference between Ic2 (designated as leaving Q2-C)
>> and Ic1 (designated as entering Q4-C). Since both are positive and
...
>> about matched, their difference can take either sign.
>
> You guys are assuming that the active load perfectly mirrors the
> current in diff branches aren't you?

Well, if I was assuming that, I would have said that Ic1 and Ic2
were matched rather than "about matched".

> I used to believe that the current would flow bidirectionally 'till
> I wondered where I'd get that reverse current. You both are welcome
> to simulate this circuit in Spice and try for yourselves.

It is obvious that either Q2 or Q4 can have the greater
collector current. There's your reversal. Why should
we need Spice to discern this?

> I pulled out an old NPN diff stage so my circuit's upside down. Same
> thing.

If you mean to contradict with a simulation, you will have
to show your circuit, its input, and the observations that
you claim are at odds with my conclusions.

>>> Included is the schematic of Fredericken's(Intuitive IC Op Amps) basic op-amp sans stage 3 - emitter follower unity gain output.
>>> How is Iout converted to voltage?
>>
>> You can think of Cc and that (nameless) rightmost transistor
>> as an integrator (if Early voltage is infinite) or as a high-gain
>> stage with a very low frequency pole (otherwise).
>>
>>> In Frederickson's text:
>>> "The second stage of the basic op-amp converts this current back into a voltage Vout, that will become the output voltage of
>>> the op amp. An internal capacitor, Cc, is the component that does this conversion of current to voltage."
>
> Cc is a pole. Nothing more. I've got no Miller stage at all and I
> can get a voltage across a resistor which is the same thing you get
> if you replace the active loads with resistors.

Cc is a feedback element in an inner loop here. In order
to find where the excess phase shift of this circuit happens,
it will be necessary to treat Cc as something more than
just "a pole".

>> That seems to eliminate the role of that nameless transistor.
>> Since it functions to hold its base at nearly constant voltage,
>> by driving the top end of Cc, that is quite an omission.
>
> The Miller stage bjt is for voltage gain. I'm repeating myself often
> here.

It is worth noting that it also serves to keep the collector-base
voltages of Q1 and Q2 at about the same values. This is
important for input offset stability. Your circuit without the
post-diffamp gain stage will suffer a funky step response
due to thermal effects that this stage will not show.

>>> It would seem that this statement has answered my question. How is Vo calculated and how can Iout be negative? Active8, I'm
>>> speaking wrt Frederickson's text & schematic below. He clearly states Iout can be bi-directional.
>
> Show me.
>>>
>>> First I want to make sure about the bi-directionality of Iout - it seems there is disagreement here from other posts.
>>
>> Anybody who disagrees with the bi-directionality is mistaken.
>
> Show me.

Whenever Vo slews upward faster than is needed to supply
Qnameless base current, it is because Iout is flowing toward
the diffamp.

>>> How would you characterize stage 1's output @ Vo'. Is it:
>>> 1.) a current pump w/ Iout(V+ - V-) = Ic2 - Ic1 & 2Ic < Iout < 2Ic
>>
>> Ok. We usually call that a current source.
>>
>>> 2) a high impedance voltage source Vo' = Av(V+ - V-)
>>> 3) something else
>>>
>>> If it is 2, I would appreciate it if you can answer the following:
>>>
>>> 1. How do you compute Vo'?
>
> Av = 40Ic_Q2(Ro_Q2 || Ro_Q4 || Ri_Qmiller) something like that. 1st
> order quess.

You seem to have ignored the additional gain that occurs
thru the Q1,Q4 path. Perhaps you do not understand the
role of the Q3,Q4 current mirror here. If you did, then
the Iout bi-polarity would not be in controversy.

> <snip>
>>
>>> Ga Tech/Penn State/MTU/UNLV/... lectures always have DC analysis of the differential amplifier active load end w/ Iout(V+ - V-)
>>> =
>>> Ic2 - Ic1 and stop short of stage 2 conversion of current to voltage. However, Frederickson's "Intuitive IC op-amps" mentions
>>> the
>>> cap is where the conversion takes place. Other - specifically Active8 - may choose "3) something else" because he believes that
>>> Iout can't be negative.
>
> Because there's nowhere to get it from!

What about Q4? Do you think it is in cutoff when Vo
is mid-rail?

...

>>> +Vcc +Vcc
>>> o o
>>> | |
>>> | |
>>> 2 Ic = Bias Current Io = Bias Current
>>> | |
>>> | |
>>> | |
>>> o------o-----o |
>>> | | |
>>> |< >| o-------o----o Vo
>>> Vin(-) -| Q1 Q2 |- Vin(+) | |
>>> |\ /| Cc --- o
>>> |Ic1 Ic2 | --- |
>>> | | Vo' | |/
>>> | o----------------------o---o-|
>>> | | Iout = Ic2 - Ic1 (+/- 2 Ic)|>
>>> | | o
>>> | | |
>>> | | Ic1 |
>>> | o |
>>> | |/ |
>>> o----o---o-| Q4 |
>>> | | |> |
>>> | | Ic1 o |
>>> | o | |
>>> | |/ | |
>>> |--| Q3 | |
>>> |> | |
>>> | | |
>>> -------o |
>>> | |
>>> | |
>>> -Vee -Vee
>>> (created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de) 

-- 
--Larry Brasfield
email: donotspam_larry_brasfield@hotmail.com
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