Re: Is 50 MHz doable for a complete newbie?

From: Tobias Weingartner (weingart_at_cs.ualberta.ca)
Date: 02/19/05 

Date: Sat, 19 Feb 2005 19:13:40 +0000 (UTC)

In article <6rve111eqo2ou385oa50spkg4kof17ci2r@4ax.com>, John Larkin wrote:
>
> 50 MHz with conventional CMOS logic parts isn't bad. But spend a few
> bucks more for a 4-layer (or more, if you need it) board with a solid
> ground plane and a single or split power layer. After that, just keep
> all the traces short (don't trust an autorouter! They tend to give
> your most critical signals the Grand Tour of the board.)

I'll have to look into that. I'm not too well versed with anything
beyond 2 layers...

> Sprinkle surface-mount bypass caps around, with vias to the ground
> plane and the power plane/islands. Maybe four or so per chip per
> supply voltage, and a few more here and there. Contrary to folklore,
> you don't need one per power pin, nor do they have to be super-close
> to the power pins. The best bypass cap is the capacitance between the
> power and ground planes, so make that dielectric layer as thin as the
> board house allows.

Hmm... so putting a cap onto each power/gnd pin on the cpu is not
100% necessary?

> Plan your FPGA pinouts to minimize trace lengths and crossovers, and
> contribute to the general beauty of the board.

Hoping to do that. :) But beauty without working won't help. :)

> Use series resistors (small surfmount arrays) in the lines to the
> SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
> memory.

Hmm... this I do not understand... guess I have to go see about
some existing circuit to see what they are doing. You mean think
of the data/address/control lines like a coax cable, and the 33 ohm
terms like the 50 ohm terminater I used to use when doing coax
ether?

> Which CPU and FPGA are you going to use? Bring out a few unused CPU
> port pins and FPGA pins to test points.

I'm looking at an eZ80190 (VQFP-100) from Zilog, as well as an
XC3S400-4TQ144I from xilinx. Along with that, I'm hoping to put
together 8MB of flash, and 8MB of SDRAM. I'm thinking an XC9500XL
series should be able to handle at least the configuring of the
FPGA from the flash. (I'd like the flash to do double duty as flash
for the cpu as well as the fpga).

I'm not 100% sure if the XC9500XL would be good enough to handle
the logic for interfacing to the SDRAM for the CPU, and possibly
the FPGA as well (I know I can do it on the FPGA, but I'd rather
keep the FPGA "separate", something that another user can program
and not screw up the cpu completely).

My application needs the cpu, and the '400 FPGA from xilinx is big
enough and cheap enough for the other parts. I may be able to fit
my final verilog design into the '400 with it's own RAM blocks, but
I'd like to access the SDRAM for some of the parameters/"registers"/ram,
as that would reduce the pressure on the '400 significantly.

Basically, if the XC9500XL could arbitrate between the two (fpga/cpu),
and handle the sdram nastyness (timing, refresh/etc), and present
a SRAM type of interface to the FPGA/cpu, I think the rest could
be hacked together by me. :)

The FPGA needs to interface with the SDRAM (to read/write things).
All the unused pins will be brought out to other electronics, such
as ADCs, DACs, SCRs, etc, to interface with the outside world. 

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