Re: Is 50 MHz doable for a complete newbie?
From: Tobias Weingartner (weingart_at_cs.ualberta.ca)
Date: 02/20/05
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Date: Sun, 20 Feb 2005 04:22:17 +0000 (UTC)
In article <e7cf11d9amsilfb949g4sr70igauusmm5q@4ax.com>, John Larkin wrote:
>
> There are lots of ads in the backs of the electronics mags (EE Times,
> ED, EDN) these days for cheap multilayer boards. What you're intending
> sounds pretty much impossible to me on less than 4 layers, reasonable
> on 6.
Oh, getting 4-6 layer boards done ain't that hard... I can get them
done through the university, or even expresspcb/etc. I guess I'm going
to shoot for 4, and not be surprised if I hit 6. :-)
> Not if you have decent power and ground layers. We just did a board
> with a 32-bit uP, an XC2S600 BGA, and four 16 mbit fast srams; 4 caps
> for the CPU, 4 for fpga core, 4 for fpga i/o, two per ram. Works great
> at 55 MHz + 100 degrees C.
I'd love to know more if possible. :) I'm always looking for examples
that I can look at, and imitate.
> >> Plan your FPGA pinouts to minimize trace lengths and crossovers, and
> >> contribute to the general beauty of the board.
> >
> >Hoping to do that. :) But beauty without working won't help. :)
>
> Beautiful layouts always work better!
Good to know. Beauty is what I'll go for.
> >> Use series resistors (small surfmount arrays) in the lines to the
> >> SDRAMS; try 33 ohms maybe, close to the CPU or FPGA driving the
> >> memory.
> >
> >Hmm... this I do not understand... guess I have to go see about
> >some existing circuit to see what they are doing. You mean think
> >of the data/address/control lines like a coax cable, and the 33 ohm
> >terms like the 50 ohm terminater I used to use when doing coax
> >ether?
>
> Large arrays of drams are distributed capacitive loads and signals
> tend to ring. The series Rs give you the option to trade off a little
> speed for damping. But why the hassle of sdram? Unless you need a lot,
> sram is a lot more friendly. You can get 1Mx16 superfast sram in a
> package nowadays.
At that point, I'd be looking at putting 4 of those on the board. I
suppose that's not too much. Along with some logic to address them
in a byte wise fashion.
> >> Which CPU and FPGA are you going to use? Bring out a few unused CPU
> >> port pins and FPGA pins to test points.
> >
> >I'm looking at an eZ80190 (VQFP-100) from Zilog, as well as an
> >XC3S400-4TQ144I from xilinx. Along with that, I'm hoping to put
> >together 8MB of flash, and 8MB of SDRAM. I'm thinking an XC9500XL
> >series should be able to handle at least the configuring of the
> >FPGA from the flash. (I'd like the flash to do double duty as flash
> >for the cpu as well as the fpga).
>
> That should work. How will you load the uP code into the flash?
Ideally I'd like the cpu to do it (more logic) with a monitor type
of program. Serial download of new firmware. But until I get to
that point, jtag will likely have to be it.
> Sounds doable. But if this is your first shot at a thing like this,
> budget for a second pass at the PCB layout, but try very hard to get
> it right the first time.
I think I'll be budgeting for 3 in the end.
-- *----------------------------------------------------------------------------* | Tobias Weingartner | Unix Guru, Admin, Systems-Dude, ... | | Apt B 7707-110 St. |-----------------------------------------------------| | Edmonton, AB T6G 1G3 | %SYSTEM-F-ANARCHISM, The OS has been overthrown | *----------------------------------------------------------------------------* [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax
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