Re: Delay without affecting pulse width

From: Kitchen Man (nannerbac_at_yahoo.com)
Date: 03/13/05 

Date: Sun, 13 Mar 2005 12:01:24 -0700

On 10 Mar 2005 21:32:34 -0800 in sci.electronics.basics,
stratus46@yahoo.com wrote msg
<1110519153.984390.183960@g14g2000cwa.googlegroups.com>:

>Not what I had in mind, no. The OP wants a delay on both the leading
>and trailing edge, I.E. maintain the original pulse width, just delay
>it. Think of this as a 1 bit digitizer and the shift register is the
>memory. If your clock is good, no temperature variations, very
>predictable and pretty simple. Take the output from different bit
>counts and/or vary the clock rate for different/multiple delays.

I guess I didn't explain myself clearly. I don't think there is a
system clock, so to use this approach, a system clock has to be
developed and synchronized to the release pulse. 

-- 
Al Brennan