Re: coutdown 555 timer values?

John Fields wrote:

The tricky part is shortening up that first 555 pulse in astable mode
(which is longer than the rest because of the need to get the timing
cap up to 2/3Vcc from 0V (instead of 1/3Vcc) on startup) and getting
all the shift register outputs to go high on startup.

I think this is easily solvable by using a pair of capacitors in series across the supply as the timing capacitor. If you use one capacitor about twice as large as the outer, the mid point voltage will begin the first timing cycle at about 1/3rd of the total voltage, just like it will be at the end of the next cycle.

Using something like three HC74's would solve the "start high" problem
by using the Qbars as outputs, using their SET inputs for POR, and
using their RESET inputs to start the timing sequence.  Getting rid of
the extended first pulse problem could be done by using a couple of
555 as monostables in a ring counter.

Schematic on abse as "555 countdown timer (from seb), or:

 news:poece11tgcals43avpikokbd73ubinh5kj@xxxxxxx


Then, of course, there's always:

VCC>------+----+
| | V+ | [RT] | | | [10K] [R7] +----|-\ | | | | >--+-->180s
+----|----|+/ | | V+ | | | [R6] | [10K] | +----|-\ | | | | >--+-->150s
+----|----|+/ | | V+ | | | [R5] | [10K] | +----|-\ | | | | >--+-->120s
+----|----|+/ | | V+ | | | [R4] | [10K] | +----|-\ | | | | >--+-->90s
+----|----|+/ | | V+ | | | [R3] | [10K] | +----|-\ | | | | >--+-->60s
+----|----|+/ | | V+ | | | [R2] | [10K] | +----|-\ | | | | >--+-->30s
+----|----|+/ | |
| +----D
[R1] | G--+
| [CT] S |
| | | |
GND>------+----+----+ |
_ |
R/T>---------------------+

In this circuit we use six comparators with references derived
ratiometrically from Vcc, which will make the circuit insensitive to
longish-term variations in Vcc.  The circuit works by applying a short
positive pulse to the gate of the MOSFET, which discharges CT and
forces all of the inverting (-) inputs to the comparators lower than
the reference voltages on their non-inverting (+) inputs.  This will
cause all of the outputs to go high.  Then, when CT charges it will
rise through  each of the reference voltages on the + inputs
sequentially, turning each of the  comparators ON sequentially,
forcing, and holding, their outputs low, one at a time.

In order to determine the widths of the various outputs we can use 

                   Vcc
     T = RC ln ----------- = kRC
                Vcc - Vth

to determine what the voltages will be on the - inputs of the
comparators at the times we're interested in.


This is a lot simpler than a whole batch of 555s running in parallel.
.

Relevant Pages

  • Re: coutdown 555 timer values?
    ... which will make the circuit insensitive to ... >> forces all of the inverting inputs to the comparators lower than ... >> rise through each of the reference voltages on the + inputs ... John Fields ...
    (sci.electronics.basics)
  • Re: PWM with SG3525
    ... >I have a PWM circuit with SG3525 and need to modify the circuit so ... Bias current into the C timing pin is between 2 and 20uA, ... operation, with outputs operating out of phase, the oscillator needs ... The internal oscillator has a fairly simple internal structure, ...
    (sci.electronics.design)
  • Re: 74HC123 and long pulse
    ... changing the timing in an analog circuit is ... If you go analog, you must be sure it is right before going ... Most small micros have severe limitations in registers, instruction set, etc. ...
    (sci.electronics.design)
  • Re: Debouncing....at About 1Mhz
    ... both one-shots is timing out? ... The problem, as stated, requires a circuit to operate in four ... because the four states require two bits of state information. ... kind of one-shot to handle that timing, ...
    (sci.electronics.design)
  • Re: Debouncing....at About 1Mhz
    ... one-shots is timing out? ... kind of one-shot to handle that timing, ... I posted a simple, fast circuit that works, is hazard-free, and has ... The first such glitch clocks the r-c filtered data into the ...
    (sci.electronics.design)
Loading