Re: coutdown 555 timer values?

On Tue, 26 Jul 2005 11:36:27 -0400, John Popelish <jpopelish@xxxxxxxx>
wrote:

>John Fields wrote:
>
>> The tricky part is shortening up that first 555 pulse in astable mode
>> (which is longer than the rest because of the need to get the timing
>> cap up to 2/3Vcc from 0V (instead of 1/3Vcc) on startup) and getting
>> all the shift register outputs to go high on startup.
>
>I think this is easily solvable by using a pair of capacitors in
>series across the supply as the timing capacitor. If you use one
>capacitor about twice as large as the outer, the mid point voltage
>will begin the first timing cycle at about 1/3rd of the total voltage,
>just like it will be at the end of the next cycle.

---
Yeah, that's clever!
---

>> Using something like three HC74's would solve the "start high" problem
>> by using the Qbars as outputs, using their SET inputs for POR, and
>> using their RESET inputs to start the timing sequence. Getting rid of
>> the extended first pulse problem could be done by using a couple of
>> 555 as monostables in a ring counter.
>>
>> Schematic on abse as "555 countdown timer (from seb), or:
>>
>> news:poece11tgcals43avpikokbd73ubinh5kj@xxxxxxx
>>
>>
>> Then, of course, there's always:
>>
>> VCC>------+----+
>> | | V+
>> | [RT] |
>> | | [10K]
>> [R7] +----|-\ |
>> | | | >--+-->180s
>> +----|----|+/
>> | | V+
>> | | |
>> [R6] | [10K]
>> | +----|-\ |
>> | | | >--+-->150s
>> +----|----|+/
>> | | V+
>> | | |
>> [R5] | [10K]
>> | +----|-\ |
>> | | | >--+-->120s
>> +----|----|+/
>> | | V+
>> | | |
>> [R4] | [10K]
>> | +----|-\ |
>> | | | >--+-->90s
>> +----|----|+/
>> | | V+
>> | | |
>> [R3] | [10K]
>> | +----|-\ |
>> | | | >--+-->60s
>> +----|----|+/
>> | | V+
>> | | |
>> [R2] | [10K]
>> | +----|-\ |
>> | | | >--+-->30s
>> +----|----|+/
>> | |
>> | +----D
>> [R1] | G--+
>> | [CT] S |
>> | | | |
>> GND>------+----+----+ |
>> _ |
>> R/T>---------------------+
>>
>> In this circuit we use six comparators with references derived
>> ratiometrically from Vcc, which will make the circuit insensitive to
>> longish-term variations in Vcc. The circuit works by applying a short
>> positive pulse to the gate of the MOSFET, which discharges CT and
>> forces all of the inverting (-) inputs to the comparators lower than
>> the reference voltages on their non-inverting (+) inputs. This will
>> cause all of the outputs to go high. Then, when CT charges it will
>> rise through each of the reference voltages on the + inputs
>> sequentially, turning each of the comparators ON sequentially,
>> forcing, and holding, their outputs low, one at a time.
>>
>> In order to determine the widths of the various outputs we can use
>>
>> Vcc
>> T = RC ln ----------- = kRC
>> Vcc - Vth
>>
>> to determine what the voltages will be on the - inputs of the
>> comparators at the times we're interested in.
>
>This is a lot simpler than a whole batch of 555s running in parallel.

---
Yup, and here are the values for the passives:

VCC>------+----+
| | V+
| [787K] |
| | [10K]
[499] +----|-\ |
| | | >--+-->180s
+----|----|+/
| | V+
| | |
[232] | [10K]
| +----|-\ |
| | | >--+-->150s
+----|----|+/
| | V+
| | |
[340] | [10K]
| +----|-\ |
| | | >--+-->120s
+----|----|+/
| | V+
| | |
[511] | [10K]
| +----|-\ |
| | | >--+-->90s
+----|----|+/
| | V+
| | |
[750] | [10K]
| +----|-\ |
| | | >--+-->60s
+----|----|+/
| | V+
| | |
[1050] | [10K]
| +----|-\ |
| | | >--+-->30s
+----|----|+/
| |
| +----D
[1620] |+ G--+
| [100µF] S |
| | | |
GND>------+----+----+ |
_ |
R/T>---------------------+

I haven't shown any hysteresis, but a megohm or so from each of the
comparators' outputs back to their non-inverting inputs ought to take
care of it without upsetting the thresholds too much, considering that
that 100µF is +/- 10% at best.

Unfortunately, it turns out that the OP needed something other than
what he asked for, so he won't be able to use the circuit. :-(

Fortunately, it was a fun exercise to linearize that cap's response
without having to resort to an active current source! :-)

--
John Fields
Professional Circuit Designer
.

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