Re: Augh! WTF 'megabaud'?

On Thu, 11 Aug 2005 02:26:40 GMT, Rich Grise <richgrise@xxxxxxxxxxx>
wrote:

>On Sun, 07 Aug 2005 12:12:23 -0700, John Larkin wrote:
>
>> On 7 Aug 2005 03:10:06 -0700, "PeteS" <ps@xxxxxxxxxxxxxxxxxxx> wrote:
>...
>>>For SPI, (Mot style, anyway), you need MOSI (Master Out, Slave in),
>>>MISO, Clock.
>
>Yeah, that's the one. :-)
>
>> The only thing you can do when you use an SPI-claimed serial device is
>> read the datasheet *very carefully*. Being lucky doesn't hurt, either.
>
>Yes, and I've been doing just that, against the day that I find out that
>I have to make up my own spec for my own design, based on meeting all
>of the other chips' worst-case setup and hold times. I'm not too
>worried about clock rate, bitbanging. :-)
>
>Other than that, I get the distinct impression (from my studies and
>feedback) that I can do pretty much any thing I want to. <leer, snort> >:->
>
>With a 4 MHz clock, a reasonably well-written loop could maybe do
>50 KBPS. That should be fine. :-) GIVEN, of course, that I meet
>everybody else's setup and hold times, thresholds, and all that
>connect-the-dots stuff.

Just this afternoon we were discussing whether it was worth using the
dedicated SPI interface in the 68332 to program a couple of Xilinx
chips (essentially SPI in slave serial mode) or whether to just keep
bit-banging like we usually do. We checked some old code and it looks
like we're banging about 600 kbits/second, with a 20 MHz CPU clock. We
copied (we call it "cached" to sound more professional) the code from
eprom into CPU internal ram to speed things up, and the code is fairly
tweaked assembly.

We're planning a product with maybe 10 mbits of Xilinx configuration
data, 15 seconds or so to configure, so the hardware SPI thing starts
to look interesting there.

Hey, if you had an fpga that was partially configurable, you could do
a sort of bootstrap operation, serially load a small block that lets
you parallel-load the rest.


John

.

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