Re: luxeon led dimmer circuit
- From: Bob Monsen <rcsurname@xxxxxxxxxxx>
- Date: Wed, 05 Oct 2005 16:18:58 -0700
On Sun, 02 Oct 2005 19:10:09 +0100, andy wrote:
> I've built the following circuit on breadboard as a dimmer circuit for 3
> luxeon III Star ultrabright LEDs:
>
> http://www.niftybits.ukfsn.org/electronics/luxeon-dimmer.png
>
> any comments welcome. It does work at the moment, but when the battery
> is low, the maximum current drops from 0.9 A to 0.7 A, and the op-amp
> swings near to the top rail. The one thing I'm thinking of changing
> before I solder it up is to change the 1 ohm sense resistor for a lower
> value (maybe 0.5 ohm) so that the transistor has a bit more headroom to
> work with, which should cure this I think.
>
> The LEDs are /very/ bright by the way - 3 of them are enough to light a
> small room well enough to read by. The light is a bit unkind on the
> eyes, but not too bad. 3 at full current are about equivalent to an 11
> Watt energy saving fluorescent light bulb, which puts them in roughly
> the same bracket as far as efficiency goes.
Another way to control brightness is to use what is called a PWM circuit.
Basically, you give your pass device a pulse every once in a while, and
control the percentage of time it is on. Since you aren't just burning up
energy with a resistor, it is often cooler and more efficient.
A simple circuit for this consists of a cmos 555, an N-channel JFET, a
cap, and a pot:
-----------------------o--------------o--Vcc
| |
| ||--'
.--------. | || J1=BF245B
.------+Vss Vcc+----' .->||--.
| | CN555 | | |
| | | | |
| | tr & th----------o------o
| | | R=470 |
| .---+OUT DISC+---o-\/\/\/\--------o
| | | | | ^ |
| | '--------' '----' |
| | |
| | |
| '-Gate of logic level NMOS ----- C=1uF
| -----
| |
-o------------------------------------o--Gnd
Call the current through J1 'I'.
The period is going to be the sum of the charging time
Tc = (1/3 * Vcc) * C / I
and the discharge time is
Td = R*C*ln((2Vcc - 3RI)/(Vcc - 3RI))
The duty cycle, which is what you are interested in, will obviously be
Tc/(Tc+Td)
since OUT is high during Tc.
The odd thing is that if you simplify this, the duty cycle doesn't depend
on the size of the capacitor; it only depends on vcc, Id(J1), and R. Thus,
you can pick a cap that is small enough so you don't see a flash, but not
too so the pass transistor requires too much dynamic current. The duty
cycle defined by this monster:
Vcc
D = ---------------------------------------------
Vcc + 3 R I ln((2 Vcc - 3 R I)/(Vcc - 3 R I))
So, when R is 0, D is 1, and when R is Vcc/3I, D is 0
That means that when R=Vcc/3I, the thing will simply stop, with output
low. The reason is that the discharge pin won't be able to pull the
trigger pin lower than Vcc/3. When R=0, it won't take any time to
discharge the timing node (well, almost no time) so D <- 1.
The N-JFET will vary as to how much current it will source in this
configuration. If it is sourcing too much, put a small resistor between
the drain and the point where the gate attaches; this will lower the
current. However, you need to make sure that your new resistor times the
current isn't bigger than Vcc/3. If it is, the output will get stuck
trying to pull the timing cap up to 2/3 Vcc, which means output will be
high and your pass transistor will be on all the time.
If you can't find a JFET, you can use a couple of PNP transistors as a
reasonable current source, like this:
--------o---------o-------vcc
| |
| [Rxx]
| |
e |
b--------o
c |
| e
o--------b
| c
| |
[Ryy] '----- current out
|
GND
Rxx sets the current to near I = 0.615/Rxx. Ryy should provide 1/10 of the
current through Rxx, so
Ryy = 10*(Vcc - 1.3)/I
---
Regards,
Bob Monsen
.
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- From: andy
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