Re: EPROM to RS232

On Wed, 09 Nov 2005 08:00:32 -0500, Bart wrote:

> I'd like to build a handheld unit that will send what is on an EPROM over
> RS232 to a PC.

If you can deal with a parallel port, it'll be easier. The port already
has enough signals to transfer a byte at a time, so you can get away with
fewer parts. You could also probably power the device from the port, which
provides signals at 5V. In fact, you could clock the address counter from
the PC, wait a bit, then retrieve the data from the data port.

Using a serial port means having a UART, or alternately a device to
simulate one. UARTs are usually designed to be driven by a processor.
However, using a 16 bit parallel-in serial-out buffer, you can probably
simulate a 10 bit transmission. RS232 wants the line to be logic 1 until
the 'start bit', which goes to 0, followed by the data bits, followed by a
logic 1 'stop bit', and more logic 1s until the next character. It also
likes low to high bit ordering. So, load bits 1111xxxxxxxx0111
into the 16 bit register, and shift the low order bits out. Make
sure the serial in bit is set to 1, to keep the line idle. The data would
go to an RS232 driver chip, like a MAX232 or something.

One problem is that using a 555 for the clock is going to be tricky, since
it won't be very stable over time. RS232 assumes synchronized clocks on
both sides, and won't tolerate more than about 5% of deviation. Thus,
you might have to tune the clock occasionally. Using a crystal oscillator
is generally a better way to go. Since you can get a crystal that is
38.4k, you might use that as your bit rate. Clock your counters (the
number of bits in the counter should be the number of address bits in the
eprom, plus 4 (or 5, see below)) with an oscillator built from that
crystal (an unbuffered inverter is a good way to go), and use D4 on from
the counters to address the EPROM. You will probably want to use
synchronous counter, or you'll get glitches in the address lines. Use the
D0 bit to load the next value into the shift register, since when that
changes, the eprom will have had a bit time to settle since the address
increment.

Use a modem control signal to reset the counters to 0... also, if you use
an extra bit in the counter at the top, you can use that bit to inhibit
the counting, and signal completion using a modem signal. Otherwise,
you'll get wraparound.

These are just off-the-cuff ideas, you can clearly improve on them...

---
Regards,
Bob Monsen

There once was a man from Hornepayne,
Who tried to transform the whole plane,
It bent a meridian
So it wasn't Euclidean,
And frustration drove him insane.
- Anonymous
.

Relevant Pages

  • Re: testbench for a microprocessor
    ... ENTITY mp IS PORT ( ... Clock: IN STD_LOGIC; ... -- control signals ... MemWr: OUT STD_LOGIC; ...
    (comp.lang.vhdl)
  • Re: simple state machine
    ... to let other people understand the code) for your states and signals, ... and from signal to port is the same problem. ... If i make counter with clock, ... How can I check that some state was active for example second times? ...
    (comp.lang.vhdl)
  • Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic -
    ... "input setup/hold time" is the time required before a clock edge to ... Setup time is the time for the signal to be stable prior to ... live in isolation it is connected to outside devices that may have timing ... the calling module and in the signals used in the submodule. ...
    (comp.arch.fpga)
  • Re: SPI unterminated
    ... the plan is to run the SPI signal ... I would put a series resistor at the clock driver (there is ... You may want to put ground pins adjacent to the clock pin to ... But if you would rather be safe than sorry, or if the signals are going ...
    (sci.electronics.design)
  • Re: Newbie question about Wait for X and ModelSim
    ... Just to confirm the reason why I wanted to included a time delay. ... was modelling in VHDL a buffered sampled input bit to an output bit. ... The input sample is taken on the rising edge of a clock signal and the ... learning step was to move these signals from pins to internal signals ...
    (comp.lang.vhdl)