Re: Transmission Gate question

Angmor <angmor@xxxxxxxxx> wrote:

: My question is... How can I determine the output voltage? I can't
: determine the transistor mode or currents without the output voltage,
: and if I can't do that I cannot determine the on resistance. I am not
: asking for an answer to my problem, I would just like a nudge in the
: right direction if possible. This problem is driving me crazy.

Not true. You only need the gate voltage and the source voltage
to determine the current. You can "guess" at the drain voltage and see
what happens. What you will find is that the drain voltage doesn't matter
(in this case.)

Let's look at the NMOS first. NMOS vg = Vdd. Suppose NMOS Vs
(input signal) = 0V. NMOS Vgs = Vdd. Let's consider 3 possibilities for
NMOS Vd (output signal): Vd = Vs = 0V, Vd = Vdd, and Vd is somewhere
between Vdd and 0. If Vd = 0V, Vds = 0V. With Vgs = Vdd, and Vds = 0V,
the NMOS device is in the linear region with a Vds of 0V, which implies
that Id = 0 (something that you would expect of a floating transmission
gate, right?.) Now suppose that Vd = Vdd. Now Vds = Vdd. With Vgs =
Vdd, and Vds = Vdd, the NMOS must be in saturation, because Vds > Vgs -
Vt. In saturation, Id = beta/2 * (Vgs - Vt)^2. This means that a current
would be flowing from drain to source, which is not something that you
would expect (in the steady state) of a floating transmission gate. Now,
suppose that Vd = Vdd - Vt - delta (where delta is some very small
number.) With Vgs = Vdd, and Vds = Vdd - Vt - delta, the NMOS is in the
linear region, and has Id = beta * (Vgs - Vt)*Vds - Vds^2/2. There will
be a non-zero current flowing from drain to source, which, again, is not
something you would expect from a floating transmission gate.

I'll leave the analysis of the PMOS to the reader, but it is
nearly identical. In my reasoning, I assumed that the "output" (i.e. one
side) of the transmission gate was floating. I forget if this was the
case in your original problem. What I mean by floating is that it is
connected to a load that is high impedance at DC. THis could be an actual
open circuit, or something that looks like one at DC (like a capacitor
connected between the output and ground, which is the case if it is
driving the input of a CMOS gate.) If this is not the case, the analysis
is a little diffrerent, but you can use the same techniques to prove this
to yourself.

Hope that helps,

Joe

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