Re: about the arrow direction of bulk of pmos and nmos

On 5 Feb 2006 18:57:04 -0800, Winfield Hill
<Winfield_member@xxxxxxxxxxx> wrote:

John Larkin wrote...

The conventional power fet symbol is a mess. We draw fets that look
like regular NPN or PNP transistors, but we add the insulated gates.
It's easier to resolve and far more intuitive.

|
|__|
| |
-----| |
| |
|-> N type
|
|

It's a mess allright. That symbol conflicts awkwardly with the
appointed symbol, with it's substrate diode going the other way.

*I* appoint the symbols. Mine looks like, and behaves like, an NPN
transistor with an insulated gate. I don't have to show the substrate
diode any more than an NPN has to show the b-e zener.


. |
. |__|
. | |
. -----| |<-,
. | | |
. |--+ N type
. |
. |


But the substrate diode is source-to-drain, not halfway up, and it's
unaffected by the gate. And there are just too many bits and pieces
for this version to look right on a well-proportioned schematic.

John


.

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