32bit multiplication using TTL logic

I want to design what would have been a super computer in 1975, using
parts that would have been "easily" available. Several people have
done this already, just not on an insane scale. My favorite is the
Magic-1, which I'm currently designing PCBs for. It has been a GREAT
learning experience studying the schematics from the Magic-1. I never
thought much about what a computer did during the mysterious clock
cycles between instruction cycles, and now with the microcode muxes,
registers, it all just makes sense.

Any way, I need my computer to be very good at math. The magic-1 is a
16bit Add/sub/compare machine. I want to make mine capable of 32bit
operations and have a 32 bit data path.

I'm starting with 32bit multiplication because it gets 32bit addition
out of the way as well.

I threw together a diagram of a 32*32 multiplier using around 1040 AND
gates and 400 74283 Adder circuits. This schematic would be what I
think is called "asynchronous".

Once I completed my diagrams I remembered something horrible. There is
a LOT of time spent waiting for the carry-in-out propagation in the
hundreds of adders which leads me to building an adder out of XOR and
AND gates. This comes at the added expense of power consumption board
space, but should speed things up by about 250x. Could anyone suggest
the best 1 bit addition "block" with carry? Its pretty late here and
I'm starting to loose brain function.

Crazy? Remember, a few weeks ago I completed soldering 19,008 LEDs to
make a display...which I haven't finished yet... (building the drivers)

One last thought for those of you who, well, you know who you are.
Idle, what would the power consumption of some 600 odd ICs be? 20ma
per device? This just might make more heat than a pentium!

Now...for floating point... ;)

.

Relevant Pages

  • Re: 32bit multiplication using TTL logic
    ... Magic-1, which I'm currently designing PCBs for. ... gates and 400 74283 Adder circuits. ... what would the power consumption of some 600 odd ICs be? ... The IBM 704 did floating point with tubes! ...
    (sci.electronics.basics)
  • 3state/gate-based MUXes
    ... We are implementing a complex adder design with VHDL and are synthesizing it in the UMC90nm library. ... -- Design: mux ...
    (comp.lang.vhdl)
  • Re: Question about: Logic Levels in Critical Path
    ... Symon schrieb: ... If this is a Xilinx design, try looking at the design in the timing analyser tool. ... This may cause portions of the adder to be placed before the registers thus reducing the logic levels of the adder itself. ...
    (comp.arch.fpga)
  • Re: 32bit multiplication using TTL logic
    ... I want to design what would have been a super computer in 1975, ... gates and 400 74283 Adder circuits. ... carry-lookahead adder for the final carry-propagate adder in the ... hell-bent on building this out of TTL parts,there is a 4-bit TTL ...
    (sci.electronics.basics)
  • What will the next FPGA IP-blocks be?
    ... Proceedings of ISSCC a design for an incredibly fast 64-bit adder in ... A 64b adder with a single-execution cycle time of 250ps is ... energy-delay optimization framework that can rapidly optimize ... different microarchitectures in the energy-delay space. ...
    (comp.arch.fpga)