Re: 32bit multiplication using TTL logic

logjam <grant@xxxxxxxxxxxx> wrote:
: I want to design what would have been a super computer in 1975, using
: parts that would have been "easily" available. Several people have
: done this already, just not on an insane scale. My favorite is the
: Magic-1, which I'm currently designing PCBs for. It has been a GREAT
: learning experience studying the schematics from the Magic-1. I never
: thought much about what a computer did during the mysterious clock
: cycles between instruction cycles, and now with the microcode muxes,
: registers, it all just makes sense.

: Any way, I need my computer to be very good at math. The magic-1 is a
: 16bit Add/sub/compare machine. I want to make mine capable of 32bit
: operations and have a 32 bit data path.

: I'm starting with 32bit multiplication because it gets 32bit addition
: out of the way as well.

: I threw together a diagram of a 32*32 multiplier using around 1040 AND
: gates and 400 74283 Adder circuits. This schematic would be what I
: think is called "asynchronous".

: Once I completed my diagrams I remembered something horrible. There is
: a LOT of time spent waiting for the carry-in-out propagation in the
: hundreds of adders which leads me to building an adder out of XOR and
: AND gates. This comes at the added expense of power consumption board
: space, but should speed things up by about 250x. Could anyone suggest
: the best 1 bit addition "block" with carry? Its pretty late here and
: I'm starting to loose brain function.

: Crazy? Remember, a few weeks ago I completed soldering 19,008 LEDs to
: make a display...which I haven't finished yet... (building the drivers)

: One last thought for those of you who, well, you know who you are.
: Idle, what would the power consumption of some 600 odd ICs be? 20ma
: per device? This just might make more heat than a pentium!

: Now...for floating point... ;)

While some others have suggested changes like using a
carry-lookahead adder for the final carry-propagate adder in the
multiplier, I would suggest that you also look into Booth encoding (the
two techniques can both be used.) At the expense of a little bit of extra
complexity to generate the partial products, you can cut the number of
rows of partial products approximately in half. As far as using a CLA for
the final adder, I think that that's a good idea, because, if you are
hell-bent on building this out of TTL parts,there is a 4-bit TTL
carry-lookahead block (74x182?, if I recall.)

So, a Booth-Array Carry-Save portion, followed by a
Carry-Lookahead Carry Propagate portion, will be fast, and do-able, if
you're really hell-bent on making this out of TTL parts. I also agree
with the other poster that said that you really should get yourself a FPGA
development platform, but whatever floats your boat!

Have Fun,

Joe

.

Relevant Pages

  • 3state/gate-based MUXes
    ... We are implementing a complex adder design with VHDL and are synthesizing it in the UMC90nm library. ... -- Design: mux ...
    (comp.lang.vhdl)
  • 32bit multiplication using TTL logic
    ... I want to design what would have been a super computer in 1975, ... Magic-1, which I'm currently designing PCBs for. ... gates and 400 74283 Adder circuits. ... what would the power consumption of some 600 odd ICs be? ...
    (sci.electronics.basics)
  • Re: Question about: Logic Levels in Critical Path
    ... Symon schrieb: ... If this is a Xilinx design, try looking at the design in the timing analyser tool. ... This may cause portions of the adder to be placed before the registers thus reducing the logic levels of the adder itself. ...
    (comp.arch.fpga)
  • What will the next FPGA IP-blocks be?
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