Re: Bowden's BCD clock circuit
- From: John Popelish <jpopelish@xxxxxxxx>
- Date: Wed, 11 Apr 2007 23:53:40 -0300
Greg wrote:
http://ourworld.compuserve.com/homepages/Bill_Bowden/clock.htm
I don't think I explained my question properly. I understand that both
of the NAND gates are outputting high normally and either gate will
only go low when both inputs are high. So once 32+16 goes high one of
the NAND gates will go low and when 4+8 goes high the other NAND
output will go low.
My specific question refers to feeding both of these outputs into the
OR gate. My understanding is that if either one input OR the other is
high the output of the OR gate will be high.
Right. So the only way the output can go low is if both inputs are low.
So, the OR gate will
pulse when 4+8 goes high or 32+16 goes high. (On thinking about the
specific circuit now, though, when 4+8 goes high it will reset the
counter so that it will only count 12). I think I'm starting to
confuse myself, sorry if it sounds unclear.
The 4+8 gate outputs a low during the counts of 12 through 15 (those counts all contain 12, plus, possibly some bits representing values of 1 or 2). At a count of 16, bits 1,2,4,8 go low and bit 16 carries the total, so the 12 decode goes away (goes high) at that point.
Then at a count of 28, the 4 and 8 bit are both high, to add to the 16 bit, so the 12 decide goes low again till the count reaches 32, when all the lower bits reset, to be replaced by the 32 bit.
The 12 decide goes low a third time when the total count reaches 32 + 12 = 44, and stays low for 3 more counts through 47. At count 48, the 16 and 32 bits carry the total, and all lower bits are reset.
The 12 decoder goes low a 4th time when the count reaches
32 + 16 + 12 = 60, and at that point the whole counter is forced to a reset count of zero, and the whole process starts over.
The other NAND gate is a 48 decode (16 + 32) that goes low from a count of 48 through 48 + 15 = 63, but of course the count never reaches 63.
.
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