Re: Bowden's BCD clock circuit

John Popelish wrote:
....
The 12 decoder goes low a 4th time when the count reaches
32 + 16 + 12 = 60, and at that point the whole counter is forced to a reset count of zero, and the whole process starts over.

The other NAND gate is a 48 decode (16 + 32) that goes low from a count of 48 through 48 + 15 = 63, but of course the count never reaches 63.

I forgot the punch line:

So at a count of 60, both NAND gates go low for the first time.
.

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