Re: decoupling caps placement


"tempus fugit" <toccata@xxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:1b084$494eb60b$d1d89b66$25834@xxxxxxxxxxxx
Hey all;

I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin
8 and the ground is on pin 1. I know that the decoupling caps need to be
as
close to the IC as possible, but how can I connect 1 end of the cap to V+
and the other to ground when the pins are so far away? Is it sufficient to
connect 1 end of the cap to V+ and the other to a nearby ground node, or
should the cap be connected close to the actual ground pin of the IC?
Also,
do I use 1 cap for each IC? If so, (the ICs are fairly close together)
wouldn't the IC "see" the caps as being the paralleled value of the 3
caps,
thus reducing the available capacitance? I was going to use 0.1uF for the
value of each decoupling cap. Would it also be wise to use a larger (1uF
or
higher) cap in parallel?

Thanks



The purpose of the decoupling capacitors is to insure that ICs maintain
sufficient supply voltage during those times when time-varying currents flow
through the supply pins. This time-varying current is mathematically
referred to as di/dt (the rate of change of current with respect to time).

The voltage lost during these time-varying events is:

V=L*di/dt

where L is the inductance around the loop where this current flows.

The longer the path is from a capacitor to the IC then the larger L is.

However, in your case, these 4049s, due to their intrinsically-low di/dt and
the di/dt caused by their loads, should have a fairly small total di/dt for
each IC/cap combination.

So, don't worry too much about the copper paths between the IC's VCC, GND,
and the capacitors. Just keep the copper fairly thick. You can utilize any
local VCC and/or GND plane, too.

You have to know a lot about your di/dt requirements, the characteristics of
a given capacitor, and the IC supply tolerance in order to make an accurate
assessment of what type and size of capacitor to use. For your design, a
0.1uF ceramic cap per IC will work fine.

Most designers start out their designs with each IC having its own bypass
cap(s). Only after the layout process begins will we make judgments as to
whether or not the total number of caps can be reduced.

Bob

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