Re: decoupling caps placement
- From: Eeyore <rabbitsfriendsandrelations@xxxxxxxxxxx>
- Date: Mon, 22 Dec 2008 11:39:25 +0000
Tim Wescott wrote:
tempus fugit wrote:
I've got a circuit that uses 3 4049 inverters. On this IC, the V+ is on
pin 8 and the ground is on pin 1. I know that the decoupling caps need
to be as close to the IC as possible, but how can I connect 1 end of the
cap to V+ and the other to ground when the pins are so far away? Is it
sufficient to connect 1 end of the cap to V+ and the other to a nearby
ground node, or should the cap be connected close to the actual ground
pin of the IC? Also, do I use 1 cap for each IC? If so, (the ICs are
fairly close together) wouldn't the IC "see" the caps as being the
paralleled value of the 3 caps, thus reducing the available capacitance?
I was going to use 0.1uF for the value of each decoupling cap. Would it
also be wise to use a larger (1uF or higher) cap in parallel?
For that chip a 100nF (0.1u) ceramic up by pin 1, with a lead straight to
pin 1 and another one straight to pin 8 will be more than sufficient.
You can think about reducing them later -- but why? Unless you're trying
to shave deci-pennies off of the board cost, it's better to have too many
bypass caps than just enough.
Heck, I don't even always bother with one decoupling cap per chip with HC
logic !
Now consider a 40MHz '8051' with the power on pins 20 and 40 !
Graham
.
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