Re: Quad-packs in LTSpice schematics?

From: crzndog (cool_blue_dog_at_nospam_hotmail.com)
Date: 11/22/04 

Date: Sun, 21 Nov 2004 23:33:10 -0800

Not totally true anymore with highspeed designs [on the West Coast].

Quite often a schematic will contain constraints for lengths etc of traces.
The Engineer will place the contraints in the design, the PCB guy will lay
it out and then the Enginner/Signal Integrity guy will simulate using back
annotated PCB lengths/stubs.

The process is becoming more tightly coupled [and iterative] due to the
faster edge rates and clock speeds. Jitter is also becoming very important
so that margins have to be carefully watched.

"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message
news:Cp9od.47873$QJ3.43343@newssvr21.news.prodigy.com...
> Hi Kevin,
>
>>I agree that it would be wonderful to have a one really good tool that
>>does simulation and pcb all in the one go. However, invariably, PCB guys
>>like different things in the schematic capture than simulation guys do, so
>>the captures end up being different. In my view, you will never please
>>both the pcb and design people in the one system, in this universe anyway.
>>
>
> That's right. Although there ought to be a reasonable compromise somewhere
> that avoids having to key in schematics twice. Most projects, at least
> here on the US west coast work like this: Engineer designs, simulates,
> tests and draws schematic. Then it is handed to the client or boss for
> design review plus another review in a group. Afterwards a netlist is
> compiled, checked and then sent off to the layout folks. The layout is
> almost always farmed out and the layouter doesn't really care about the
> schematic. He or she just wants a netlist and package sizes, plus some
> guidance for critical stuff.
>
> Regards, Joerg
>
> http://www.analogconsultants.com