Re: Quad-packs in LTSpice schematics?

From: Joerg (notthisjoergsch_at_removethispacbell.net)
Date: 11/22/04 

Date: Mon, 22 Nov 2004 21:56:19 GMT

Hi crzndog,

>Not totally true anymore with highspeed designs [on the West Coast].
>
>Quite often a schematic will contain constraints for lengths etc of traces.
>The Engineer will place the contraints in the design, the PCB guy will lay
>it out and then the Enginner/Signal Integrity guy will simulate using back
>annotated PCB lengths/stubs.
>
>The process is becoming more tightly coupled [and iterative] due to the
>faster edge rates and clock speeds. Jitter is also becoming very important
>so that margins have to be carefully watched.
>
>

Yes, there are lots of critical layout. I had quite a few of those, too.
However, I always made sure that the layouter is experienced in this
stuff, knows why I don't want 90 degree bends and so on, and is local.
Or at least within reasonable driving distance. In Europe or Asia that
matters less because you can often hop on a fast train and in an hour
you are more than 100 miles down the 'road'.

Then I sit down with the layouter and a cup of coffee to hash out the
critical areas. This has worked well for really tricky RF designs. The
only problems I ever had were minimal. Once a layouter smoked a bit too
much. If it were pipe instead of cigarettes I wouldn't have minded.
Another had a cat and its sensitive nose didn't appreciate the fact that
we have dogs at home. When I came back from that one our dogs gave me
'the looks'.

Regards, Joerg

http://www.analogconsultants.com