Re: Protel netlist outputs

From: Simon Pea*** (nowhere_at_to.be.found)
Date: 03/21/05 

Date: Mon, 21 Mar 2005 21:58:55 +1200

"Brad Velander" <SpamThis@nowhere.com> wrote in message
news:9n0%d.728034$6l.255877@pd7tw2no...
> Ok, thanks for the clarification Simon. At first I thought
> something was drastically different in DXP and I was unaware of
> it. But they still will do a netlist, or I am betting that when
> you do update PCB, you can still generate a report of the changes
> being noted for the PCB. Same as I currently do with P99SE. After
> reading in the netlist, you are essentially in the Update PCB
> Synchronizer, with the list of changes on the screen, right click
> on the list, generate a report of the changes. Some are always
> non-circuit issues like Fiducials, test points or something else
> that isn't found in a schematic.
>

It actually generates a report every time you update the PCB I've attached
one picked at random.. they're not very big but would be a pain to have to
deal with unless you had an automated program.

> By the way, I cannot recall exactly what it is at the moment
> but ERC checking has one very big hole that it doesn't check for
> in Protel. Damn brain isn't working so well this morning but I
> know there is one check that I would have them add in to make it
> more complete, in the mean time it is not bad but only about 95%
> complete. Maybe it has even been added into DXP already, aaahhh I
> remember, checking for continuity and connection across ports and
> netnames, also single node nets regardless of pin type and
> whether you connected a wire and ran it to a port. Check that all
> the names match and that there is at least one connection across
> them if they exist. Still not foolproof though because there is
> no way for it to know there should be X number of connections on
> a net in total. OrCAD used to do a net or port name connectivity
> dump, I used to use it to try and find slightly misspelled net or
> port names because they would usually come up right close
> together on the report. They also would show a listing of
> netnames where you had connected dissimilar netnames together
> intentionally.

The ERC has been improved vastly... but there is an inconsistancy between
what I did in protel 99SE and DXP.. port directions don't match the default
ERC and inisist on being different to Protel 99SE... I also discovered that
some of the default warnings that are on in Protel 99SE don't actually
work.. mostly port stuff .. you don't notice it untill you run the same ERC
on DXP and get 50 more warnings. So that also means port ERC has been
improved too mismatched names, mis matched directions are all correctly
flagged now. Single node nets can always be flagged as "unconnected xxxx"
in 99SE or DXP. I do that by default all the time. Well if Protel could
tell how many connections should be on a net then you and I will be out of a
job.. and they wont pay as much as a room of monkeys could do the same job
:-)
miss spellings will always be a problem.. something you have to train
yourself for... you will still see it in the net list on the pannels... If
you are like me than you will also notice connections missing on the PCB as
you route it too... the advantage on manual route... its like a double
check.
Maybe Protel needs a spell guesser.. look at net names and flag those that
are close.. (thats what typos are afterall)

>
> However, as far as Ivan's enquiry goes, check the Schematic
> thoroughly, do the ERCs, update to the PCB, generate a report of
> the synchronizer updates, have the boss sign off on the
> schematic, the ERC check, then an update PCB change report and a
> DRC report. At our shop the designers add notes to either the ERC
> or the netlist/synchronizer report, indicating what the issues
> are that generated any message. (i.e. The update report is trying
> to delete a fiducial. we add a handwritten note stating that
> "fiducials are not found in the schematic". Or, "Shorting
> connection added to implement Star Point Ground", etc. )

My Boss hasn't signed off on my work in decades .. a simple peer review is
all we have... that and the original designer gets to go over the PCB and
check pin names are what he expects.
I would like to see a sign off on schematic errors and PCB errors too.. and
especially the ability to mask one particular error with an 'x' of a
different colour and say "I approve this ERC on this pin" for example saying
"pin xxx is unconnected" and have that invert the error status.. so if its
unconnected its ok.. if its connected then its an error.
Fiducials, labels and logos all have a schematic part in our library.. have
done for the last too companies I've worked for. With Protel 99SE I wrote a
BOM generator which automatically recoginised 'mechanical' parts and left
them out of the BOM. It also added tables, better sorting, support for more
than 256 chars in a column, headers, footers, and BOM splitting. Because of
that, it will be a while before updating fuilly to DXP.. we rely on the BOM
generator too much.

> After all of this our design manager signs off on our designs
> and keeps the design paperwork including these various checking
> reports in a file cabinet. For too many years he had designers
> telling him things were fine and dandy, now he holds this
> paperwork over your head and if anything is wrong it had better
> have been something that slipped through the checking without
> being caught for some reason. Then we adapt our checking and
> check lists to cover any new found issues. If you touched the
> board after the checks and cause any problems, he will have you
> by the short and curlies. He is not a nice guy but so far I
> managed to stay on his good side, others have not and I see how
> they are treated by him. I just plain don't want to be there, I
> don't need that aggravation in my life.

The checking is always the hardest part. I days gone by I've checked the
schematic and PCB with a non-technical person so that they asked
questions... but that was PCAD proir to automatic schematic/pcb
sycnronisation.. it worked but took time. Currently its up to the designer
to check the schematics and PCB a highlighter is good here (but don't use it
on the minitor.. only the paper copy :-)
We also have a 5 page check list... but its hard to transfer a check list
from a paper copy to an electronic copy.. I mostly rely on my skill .. In
saying that.. I had the first 3 boards I designed last year go into
production as Rev A, no mods, no component changes other than the original
calabration values. It shocked some people who never expect that. They
have had changes since then as new features have been added that were
outside the original spec. Not all turn out like that .. I also have a
right stinker... the choise of components wasn't so hot.. so it works.. but
leaves alot to be desired and only just meets spec (most of the time). It
was designed in a rush with components on hand and those we could get in
time. I would like to redesign it with better components now I know the
short comings but its scedualed for total replacment so unlikly to happen
now.
Im my filing cabnet I keep a printout of the schematic and PCB to be marked
up by highlighter, that way I can add changes to my design as and when
nessassary. The actual checked boards.. they are write protected as soon as
the checking and fixups and re-checking is finished.. then archived... the
only changes are to DCO's and the engineers 'working' copy. those changes
have to be approved by everyone before the become part of the next release

In saying that I think a nice addition would be to beable to compare the
previous rev, with the current rev, and have protel come up with a list of
new components, deleted components, added nets and deleted nets at any
point, I think this has been requested as part of a service pack. It is far
better than 15 ECO files and far more useful.

Guys like you Boss can be stinkers.. fortunatly the labour market in NZ is
tight and good designers are mostly imported .. so hard to come buy.. I get
treated with respect and there is a knowledge that sometimes things don't go
to plan.. theres also a knowlegde that first rev boards don't go into
production (usually)... although I'll have to be careful here.. too many
working first time and I'm going to have to do a few bad ones so they don't
forget that :-) There are also screwups from time to time... especially if
your using new components. Thats to be expected.. sometimes there are
lingering cancers too.. but we managed to find the last golden bullet.. took
over a year to find tho.. I still have one 'cancer'.. its proving difficult
to eradicate I just hope it doesn't grow but for now the customes can't see
it as we have a good work around.

Simon

>
> "Simon Pea***" <nowhere@to.be.found> wrote in message
> news:4239201d@news2.actrix.gen.nz...
> > but a default installation for Protel 2004 SP2 will output
> > edif for pcb
> > Multiwire
> > pcad for pcb
> > cupl netlist
> > Protel (1)
> > VHDL file
> > Xspice.
> >
> > that's 7.. and I only had to use two hands to count them :-)
> > There may be 12 on their web site.. but I don't use Protel add
> ons unless I
> > have a need
> >
> > The actual protel 1 and Protel 2 formats (so I added a .0 not a
> big deal)
> > are obsolete. They haven't been necessary for PCB design since
> Protel 99SE
> > so it really isn't surprising that they don't exist any more...
> I myself
> > never noticed they were gone... but it could make it difficult
> to do a
> > netlist compare... something
> > I've done from time to time to satisfy a customer on rear
> occasions.
> > I also wont mix and match packages.. so no Protel / Orcad
> mixes. Neither
> > companies really want you to use the others package so don't
> make it
> > entirely seamless. On the odd occasions I've had to convert I
> spend days
> > just checking that everything has come thru seamlessly so I
> always try to
> > avoid that.
> >
> >
> > But I have satisfied myself over the years that if the PCB DRC
> has zero
> > errors, and the Schematic ERC has zero errors then the result
> is exactly
> > what I suspect. Any warnings are individually approved. I
> also flag any
> > unconnected pin on the schematic and verify each and every one.
> I have
> > never had a board that was anything less than what was on the
> schematic.
> > For this reason I don't usually do a netlist compare and I have
> full
> > confidence in Protels results. I also flag any potential poor
> warning
> > message and feed it back to Protel in the hope something useful
> replaces it.
> > I would also stop using Protel if I lost any confidence in the
> ERC and DRC.
> > This together with a well designed schematic that is easy to
> read and easy
> > to understand and hence easy to locate errors makes the system
> foolproof...
> > but occasionally I've worn the fools hat <:-)
> >
> >
> > And that is why I have I don't generate netlists.
> >
> > Simon
>
>

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`
end

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