Re: LTspice

From: Jim Thompson (thegreatone_at_example.com)
Date: 03/21/05 

Date: Mon, 21 Mar 2005 08:13:40 -0700

On Sun, 20 Mar 2005 23:36:12 -0800, ldg <asfd@hotmail.com> wrote:

>On Sun, 20 Mar 2005 20:23:13 -0700, Jim Dynamite
><thegreatone@example.com> wrote:
>
>>dg, You harp about things that you know not about. LTSpice can run
>>ANY netlist... you're just too much the amateur to understand how.
>
>Really? :-)
>
>Didn't know I was harping. What things are you worried about? Just
>the parts about devices?
>
>I said:
>o LTspice can't handle resistor and capacitors specified with w/l and
>models. (It can actually run resistors this way with various error
>messages, but it's undocumented.) You can use undocumented features
>if you like. I usually choose not to.

Sure it can. In most Spices, it's done with subcircuits...

xR node1 node2 <stray nodes> ModelName Params: L=100u W=2u M=4
   
>
>I have run circuits in ltspice with resistors to use the graphics, but
>always have checked the results with other simulators. I like using
>multiple simulators anyway as a cross check so this isn't unusual. I
>don't like seeing the error messages LTspice gives with these models.

HSpice and "Smart"Spice tend to run NON-SPICE-STANDARD notation just
to be ass-holes and thwart portability.

But my particular schematic capture can write out netlists in multiple
templates, so I can presently write in PSpice, LVS (for any layout
editor) and SmartSpice/HSpice formats.

There IS an issue with computational notation, {...} or '...' , but
that was solved this weekend (see below).

>
>Caps don't seem to work at all specified this way, but aren't supposed
>to:
>
>Syntax: Cnnn n1 n2 <capacitance> [ic=<value>]
> + [Rser=<value>] [Lser=<value>] [Rpar=<value>]
>
> + [Cpar=<value>] [m=<value>]
> + [RLshunt=<value>]
>

Done the same way as R's...

xC node1 node2 <stray nodes> ModelName Params: L=100u W=20u (Some
nutcases use an M here, I don't, it's confusing... for segmented R's I
may adopt "S")

>**********
>
>LTSPICE test
>*********************************************************
>.model pp c cox=9e-04 capsw=2.5e-11 del=0.045e-6
>+ tref=25 tc1=22e-6 tc2=0.0
>
>*********************************************************
>
>V1 1 0 pulse(0 5 5u 1n 1n 1)
>R1 1 2 1e5
>C1 2 0 5p m=1
>R3 1 3 1e5
>C3 3 0 PP W=33.33U L=33.33U M=5
>*c3 3 0 1p m=5
>.tran 1u 15u
>
>.end
>
>*********************************************************
>
>Perhaps you can show me how to run this netlist in LTspice? It will
>run in smartspice just fine. I guess it literally "runs" in
>LTspice, but seems to give the wrong answer when the cap is specified
>by w/l and uses a typical foundry model.
>
>A lot of this is preference. I did my own layouts for years and now
>hire others to do it.

Same here.

>I've found it more accurate to design resistors
>and capacitors myself rather than giving the layout person so much
>leeway by specifying values.

Likewise. Amazing how fast a digital layout guy can screw-up an
Analog layout.

> I also use the foundry specified models
>for these devices during simulation.

(I have models for well over 100 processes/foundries.)

I'm a circuit designer, thus I THINK in values, NOT physical
dimensions. Layout people like dimensions (naturally :).

I can netlist that way (using alternate templates), backing out the
dimensions by Algebraic computations {...functions...}, but this
doesn't help the layout guy (we like to minimize human intervention
:).

So, this weekend, my oldest son wrote an executable for me that reads
in a netlist, computes all the {...} and fills in numbers for L and W,
making for a clean, untouched by human hands, LVS netlist.

After refinement, we will put it up for sale on his website.

>
>I'd be interested in how a professional organizes their workflow. How
>about teaching me a few things? As I recall you use the old Microsim
>schematic capture for layout and simulate in pspice. Is this the
>perfect solution (and we should all copy) or do you do this for some
>other reason? Do you do your own layout? What tools do you use?
>
>o No M= on Bipolars?

Spice STANDARD is A= , but the literal is assumed, not written...

Q1 C B E [SUB} ModelName 5 <<---

>
>**********
>Symbol Names: NPN, PNP, NPN2, PNP2
>
>Syntax: Qxxx Collector Base Emitter [Substrate Node] model [area]
> + [off] [IC=<Vbe, Vce>] [temp=<T>]
>
>**********
>
>I don't see it in the documentation. It may by now be an undocumented
>feature and I haven't tried this lately.
>
>Again, you're free to draw as many parallel devices and work-arounds
>as you like. I'm trying to avoid this.

Just showed you how above ;-)

>
>Thanks for any professional advice :-)
>
>Regards,
>Larry
>

                                        ...Jim Thompson 

-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
I love to cook with wine.      Sometimes I even put it in the food.
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