Re: LTspice

From: ldg (asfd_at_hotmail.com)
Date: 03/21/05 

Date: Mon, 21 Mar 2005 09:03:38 -0800

On Mon, 21 Mar 2005 08:13:40 -0700, Jim Thompson
<thegreatone@example.com> wrote:

>Sure it can. In most Spices, it's done with subcircuits...
>
>xR node1 node2 <stray nodes> ModelName Params: L=100u W=2u M=4

I used to do such things when I used pspice. It causes you to look
for ways around its limitations. Unless doing a subcircuit adds
accuracy to the simulation, it's difficult for me to understand how
doing this is better.

Once in a while I use a capacitor symbol, for instance, that calls a
subcircuit to add stray to ground. This stray is constantly present
in an IC and if you don't account for it, it can cause real problems.
It isn't needed all the time, so I just change the pointer to another
symbol in another directory and it netlists out normally.

<snip>
Done the same way as R's...

xC node1 node2 <stray nodes> ModelName Params: L=100u W=20u (Some
nutcases use an M here, I don't, it's confusing... for segmented R's I
may adopt "S")

***********

It's less confusing to place the same capacitor over and over again?
If you say so.

Lets say you were drawing a 6 bit switched capacitor mdac. This
means you have to draw 1,2,4,8,16,and 32 cap arrays (in subcircuits
perhaps?). Or you could do one of your workarounds and create the
m=<M> function yourself I suppose. Then you'd have to figure out how
to do an lvs netlist for layout. You also could simply make the caps
sequentially larger, but I know you wouldn't do that because of
matching issues and the chance of confusing the layout person.

In any case, if I have a choice of simply adding m=32 on a cap, I'll
do this instead. If the schematic capture supports iterated
instances, I've also created these arrays by adding the appropriate
instance name on the device. C[0:31]

Regards,
Larry

"nutcase"