Re: OrCad Capture

Vitaliy wrote: 
Hello,
I am using OrCAD 10.5 full suite for my school project. I'm fairly new
to it as well. I got stuck with the following problems:
1) From what I read, the schematics and pcb footprint aren't exactly
correlated. I am using Capture CIS. I could not find how to represent
PCB footprint for OPA655 (SOIC) from TI.
http://focus.ti.com/docs/prod/folders/print/opa655.html


In fact, I am not sure what the PCB footprint code for any opamp is. Or
should I use SOG.050/8/WG.something/L.something. I am not sure what 050
in SOG represents, because there are different options (i.e. 025 as
SOG.025), so I do not know which one to use. Also, if I were to use SOG

The 050 is the pin pitch in mils, .001 inches. The 8 means it has 8 pads for an 8 pin part. WG is the width of the gull-wing leads; be sure to find a foot print with a larger number here than the TI spec sheet shows for the maximum width of the part. L is the length of the molded body of the part; this really only affects the silk-screen, place outline, etc. of the foot print, so be sure to use foot print with the same or larger length than the actual part. Note that similar packages from different vendors can have different dimensions. Foot prints that have their basic dimensions specified in mm instead of inches, usually have an "m" in the numbers.

You will be advised by others, and I would second that advice, to learn to make your own foot prints, or at least to check the Orcad supplied foot prints carefully against the vendors recommended layout. It is not that hard. Foot prints are made in the Library Manager of the Layout package.

I am not sure about CaptureCIS 10.5, I use CaptureCIS 7.2, but the Capture package needs to know how to find the footprint libraries (separate from the schematic symbol libraries) in order to display the foot print when selecting parts from the database. This was/is done by creating a layout.ini file with the Layout package that contains all the foot print libraries you want to use, and then copying the layout.ini file from the Layout installation directory to the Capture installation directory.

and
http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=msoi002c&fileType=pdf
is my opamp, which dimensions am I supposed to match? Chip with the
pins or chip without the pins? Or somewhere in the middle so it is
easier to solder.

The pads in the foot print need to extend farther than the maximum spread of the leads.

2) I am also supposed to use OPA657 (SOIC)
http://focus.ti.com/docs/prod/folders/print/opa657.html. However, there
is no electrical model for it in the libraries. So, I downloaded this
opamp library from TI website. The model looks ugly though with some
pins in the middle of the chip. I can move the pins around, also it
still wouldn't look like an opamp after that. Is there a way to make it
look like opamp, not a rectangle. As far as I understand it wouldn't
matter for Layout.

I am not familiar with that part, so I don't know if it has a standard 8-pin opamp pinout, but you can use any library symbol that looks good to you and that contains numbered pins for every pin you want connected on the layout. The only information transfered from the schematic symbol to the layout is the pin numbering information that is used to create the netlist. The netlist is what transfers information about the schematic to Layout. It makes no difference what the name of the symbol is, so long as the pin numbers match the functions, AND there is a foot print available that matches the pin numbers to the right physical pins on the package (SOT-23 and TO-92 packages, amongst others, are often numbered in conflicting ways by various vendors, so be careful about this). If you don't like the look of the available symbol, and there is no standard available, make your own. I rarely use any Orcad supplied symbols, except for simple things like standard gates and op-amps.

Note that there is other information in the netlist for each part, such as the name of the footprint to be loaded (but which can be overridden once the design is in layout), the "value" of the part, the reference designator, etc.

--
NOTE: to reply, remove all punctuation from email name field

Ned Forrester        n_f_orrester@xxxxxxxx         508-289-2226
Applied Ocean Physics and Engineering Dept.
Oceanographic Systems Lab                 http://adcp.whoi.edu/
Woods Hole Oceanographic Institution, Woods Hole, MA 02543, USA
.

Relevant Pages

  • Re: this is getting crazy
    ... FPGAs, told him which pins were unassigned i/os, which ram pins he ... connectors to make the layout as easy as possible. ... physical flow of signals on the board. ... signal flow than a smaller package. ...
    (sci.electronics.design)
  • Re: MDF Baseboard
    ... resilient you want the layout, whether it has to be as cheap as possible, ... yu will have problems getting pins in but could glue the track down. ... which means you don't have a base board as such but an open frame. ...
    (uk.rec.models.rail)
  • Re: LVS problems with Assura
    ... the schematic and use Assura to DRC the layout. ... experiencing some technical difficulty to run an LVS with Assura. ... LVS would fail due to "unbounded devices" errors on ... Then it does not recognize the pins in the ...
    (comp.cad.cadence)
  • Re: "iron man classic"
    ... riuleset) with cheaper components and assemblies. ... Fireball and Capt. Fantastic all used the same PF layout just with ... What did full sized pins cost at this point in time? ... These games are ...
    (rec.games.pinball)