Nanosim with Synthesized Verilog

Hello,

I have a question about Nanosim from Synopsys. I'm in a team that does
an ASIC design - we use the IBM Cu-11 library. I want to use Nanosim to
estimate the power of my design (I can provide input vectors etc to
Nanosim). Is this possible at all?

First of all, I tried to provide the synthesized verilog (structural
verilog) files as an input to Nanosim. But, I kept getting these
errors:

Netlist compilation took 0.350 s
nanosim: ERROR: illegal # of elements (0) in netlist

Second, I tried synthesizing the same behavioral verilog files and used
dc_shell to write the output in the EDIF format. I fed this input to
Nanosim and it was able to accept the design. But, the *.edif file had
references to the standard cells from the IBM library and Nanosim
complained that it could NOT find the subcircuit definition or the
functional model of these cells.

I do have the functional model files for the IBM Cu-11 library (in
terms of the *.v files) and the *.db and *.lib files. I'm not sure how
to feed these to Nanosim. I tried the cell_lib_path option in the
config file and also, -L flag. Both don't seem to work. Does anyone how
to get this setup to work? Do I need the Cu-11 library files in a
different format? How do I indicate to Nanosim about these library
files?

Or am I in a wrong domain and should probably be looking at PrimePower
or a similar tool?

I'd be very grateful if someone answers the above questions.

Thanks in advance,
G.Sibi

.

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