Re: Nanosim with Synthesized Verilog

Hi Sibi,

I am more of an HSIM user than a nanosim user, so I may be leading you
astray. Both HSIM and Nanosim are fast-spice tools. My suspicion is
that it is expecting the spice models for the standard cells, and the
verilog/edif is used to describe the connections to complete the
matrix. Instead of giving the tool the standard cells as *.v files, see
if you have spice files available.

Good Luck.

.

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