hi all!
as someone of you knows, I'm trying to project a cascode amplifier by
myself. I finished the schematic and now I'm working on the layout (never
done before, God save me please..)
Re: OrCad Capture ... WG is the width of the gull-wing leads; be sure to find a foot print with a larger number here than the TI spec sheet shows for the maximum width of the part. ... You will be advised by others, and I would second that advice, to learn to make your own foot prints, or at least to check the Orcad supplied foot prints carefully against the vendors recommended layout.... I am not sure about CaptureCIS 10.5, I use CaptureCIS 7.2, but the Capture package needs to know how to find the footprint libraries in order to display the foot print when selecting parts from the database. ... Chip with the pins or chip without the pins? ... (sci.electronics.cad)
Re: this is getting crazy ... FPGAs, told him which pins were unassigned i/os, which ram pins he ... connectors to make the layout as easy as possible. ... physical flow of signals on the board. ... signal flow than a smaller package.... (sci.electronics.design)
Re: MDF Baseboard ... resilient you want the layout, whether it has to be as cheap as possible, ... yu will have problems getting pins in but could glue the track down. ... which means you don't have a base board as such but an open frame.... (uk.rec.models.rail)
Re: LVS problems with Assura ... the schematic and use Assura to DRC the layout.... experiencing some technical difficulty to run an LVS with Assura....LVS would fail due to "unbounded devices" errors on ... Then it does not recognize the pins in the ... (comp.cad.cadence)
LVS problems with Assura ... the schematic and use Assura to DRC the layout.... experiencing some technical difficulty to run an LVS with Assura.... LVS would fail due to "unbounded devices" errors on ... Then it does not recognize the pins in the ... (comp.cad.cadence)
