Re: Mixing addres lines of SDRAM.

From: Rune Christensen (rune.christensen_at_adslhome.dk)
Date: 07/09/04 

Date: Fri, 9 Jul 2004 10:42:41 +0200

Hello

If this were SRAM then there will be no problem with the random connections
as long as address is connected to address and data to data.

If think that mixing up the data and address lines is a bad thing. I don't
know much about SDRAM and therefore I read a data sheet about SDRAM.
It looks like you only will be able to get one address at the time when the
address lines are mixed.

Mixing up the signals is a bad thing because if there were more items
connected to the memory bus then it could give a lot of problems with the
exact locations of the data structures.

Could you tell which uP and which SDRAM chips there are used?

If the uP can make burst transfer I will have asked the designer to redesign
the circuit board because it's a bad design.

Cheers
Rune

"Wlad" <whanski@wp.pl> skrev i en meddelelse news:40EE3BEA.2030005@wp.pl...
> ear all,
>
> I have to boot-up a device based on Hitachi uP with external SDRAM
> (2x256Mb). The device was designed by somebody else and I only have to
> get it working. However there is something that bothers me very much.
> Probably to easen PCB layout the designer has mixed data and address
> lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All
> other interface signals (RAS#,CAS#,CLK,CKE,UDQM,LDQM,WE#,CE#) are
> connected correctly. While mixing data lines seems ok to me (let me know
> if I'm wrong) mixing address lines looks unacceptable.
> Here are the connections:
>
> SDRAM uP
> ------------------
> A0 A5
> A1 A4
> A2 A3
> A3 A2
> A4 A14
> A5 A13
> A6 A12
> A7 A11
> A8 A10
> A9 A9
> A10 A6
> A11 A8
> A12 A7
>
> BA0 A15 (bank select)
> BA1 A16 (bank select)
>
> Will this connection work? For the time being I know that I must forget
> burst transfers. Are there any obstacles for SDRAM in this configuration
> to work with 1-byte burst transfers?
>
> Thanks
> Wlad
> 

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