Re: Mixing addres lines of SDRAM.

From: Roger Hamlett (rogerspamignored_at_ttelmah.demon.co.uk)
Date: 07/15/04 

Date: Thu, 15 Jul 2004 11:52:04 GMT

"Wlad" <whanski@wp.pl> wrote in message news:40EE3BEA.2030005@wp.pl...
> ear all,
>
> I have to boot-up a device based on Hitachi uP with external SDRAM
> (2x256Mb). The device was designed by somebody else and I only have to
> get it working. However there is something that bothers me very much.
> Probably to easen PCB layout the designer has mixed data and address
> lines for SDRAM: i.e. pin D0 of SDRAM is connected to pin D7 of uP. All
> other interface signals (RAS#,CAS#,CLK,CKE,UDQM,LDQM,WE#,CE#) are
> connected correctly. While mixing data lines seems ok to me (let me know
> if I'm wrong) mixing address lines looks unacceptable.
> Here are the connections:
>
> SDRAM uP
> ------------------
> A0 A5
> A1 A4
> A2 A3
> A3 A2
> A4 A14
> A5 A13
> A6 A12
> A7 A11
> A8 A10
> A9 A9
> A10 A6
> A11 A8
> A12 A7
>
> BA0 A15 (bank select)
> BA1 A16 (bank select)
>
> Will this connection work? For the time being I know that I must forget
> burst transfers. Are there any obstacles for SDRAM in this configuration
> to work with 1-byte burst transfers?
>
> Thanks
> Wlad
There is nothing wrong with mixing either type of lines. All it means is
that addresses will not physically be at the expected addresses in RAM. It
is more difficult to justify on a ROM, where programming in an external
programmer will become 'hard'...
Your address lines as listed, show A0, and A1 are not present from the
micro. This means that four consecutive addresses, will all refer to the
same memory cell. I'd assume from this, that there is actually a 4byte
'latch'/multiplexor, and this is being used to select the individual
'bytes' for the processor.

Best Wishes

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