Re: 74LS90, 74LS92 and other TTL are OBSOLETE???



Well, the truth is that there is a need for ONLY 2 TTLs in the
design!!! Those are just used to give 6 diferrent subclocks from a TCXO
source. The design has also uCU, RF ASICs, and lot of other stuff like
LCD, Keyboard, etc... It's sure not a "one chip" show :))
As I see it got to use a CPLD for replacement of the 2 TTL... the
cheaper I have found until now is ~1.70$ so that's far more than
~20cents!!! I'm sure not only mine but nobodies "boss" wouldn't like to
spend 150K more than it could :)
Of course a 2U 19" rack mounted isn't so portable as a cell phone, so
why we have to shrink everything we are doing in life even if there is
plenty of room to use?
It's not look weird for you to open a 29" TV set and find out that all
it is behind that large screen is a chip with say 3 drivers a HT T/R
all in a board that could fit easy at 4.5" monitor? Yes, I know thats
the way it goes... And it's sure more economical for a production line
of >1M units / year to build your "all in one" ASIC! But at least we
must admitte that is a bit weird :)) to shrink everything, even when
there isn't a real need to do so!!!
I have done designs with FPGAs but there always a need to do it with.
Either large complex circuitry, or even dynamic reconfiguration of the
circuit needed and either space limits and total cost, the most cases
was for portable devices.
But this is not always the case...

Nice to hear your opinions on this subject..

PS Thanks for Jameco... .

.



Relevant Pages

  • Re: CQ Update: Im getting close...
    ... Way too much fun, Doc! ... has anyone mentioned to you that CQ foundations tend to shrink ... I bought black because some of my fabrics are translucent or thin, ... by ME a design on the center of the first "patch", ...
    (rec.crafts.textiles.quilting)
  • Re: Access, hide blank fields AND Captions
    ... I didn't design the db per se. ... This example shows how to shrink the label that was attached to the City ... If you have repeating columns (such as years or week numbers, ... When I print my report it has more blank fields than not, ...
    (microsoft.public.access.reports)
  • Re: Guidelines to shrink the PCB size
    ... There many ways to shrink a design. ... As examples a switching power ... 2- Now do simple PCB with few layers. ...
    (comp.arch.embedded)
  • Re: Why No Process Shrink On Prior FPGA Devices ?
    ... making a mask where everything was smaller, ... The last shrink we did was 0.18u to 0.15u in Spartan 2E for cost reasons ... update all the design PAR files to match the new timing. ... Characterizing the timing on these internal lines is a pain in the ...
    (comp.arch.fpga)