Re: 10BASE-T Clock Recovery PLL

From: Jim Thompson (thegreatone_at_example.com)
Date: 06/06/04 

Date: Sun, 06 Jun 2004 08:37:46 -0700

On Sun, 6 Jun 2004 08:08:28 -0700, Mike <mike@nospam.com> wrote:

>On 6 Jun 2004 02:11:46 -0700, Andrew Holme wrote:
>
>> See http://www.holmea.demon.co.uk/Ethernet/EthernetRx.htm for photos,
>> docs and schematics of a (just for fun) experimental 10BASE-T receiver
>> project. It's locking too slowly at the moment. Comments / advice /
>> suggestions welcome.
>
>I don't think your problem is with your charge pump transistors.
>
>I'm assuming the upper trace in your scope photo is your loop filter
>voltage. If it is, then you have at least two problems.
>
>1. At the start of the preamble, the voltage on your loop filter is hitting
>its limit. As soon as it limits, the loop response is no longer linear.
>
>2. At the end of the data, the loop is losing lock when it hits the
>checksum. If it loses lock at the checksum, it will lose lock when you
>replace the 0x55 data with real data. Your phase detector is supposed to
>handle nonuniform data, but it looks as though it's not.
>
>I have two suggestions:
>
>1. Since you've got some programming experience, why not write a
>time-domain simulator for your PLL? It's not that difficult, and with your
>C++ knowledge, you can create classes for the phase detector, charge pump,
>loop filter, and VCO. Adding nonlinearities is relatively easy, so you can
>include saturation effects and such. Start with ideal models for the logic
>and loop filter, and spend your time creating more detailed models for the
>charge pump and VCO.
>
>2. There is an initial frequency offset in your system which your step
>response is ignoring. The actual input has a ramp (frequency error) in
>addition to a step (phase error). The slope of the ramp is proportional to
>the frequency offset: larger frequency errors will result in longer lock
>times.
>
>Data recovery systems like this are typically implemented with a reference
>clock, which provides a frequency close to the data frequency until data
>begins arriving. When the preamble begins, the PLL reference is switched
>from the reference clock to the data. In many designs, the VCO is stopped
>during the switchover time, then restarted in phase with the data. The
>effect is that the initial frequency and phase errors are small, so the
>loop can lock quickly.
>
>-- Mike --

See also "DualD-PFD.pdf" on the S.E.D/Schematics page of my website
for a more robust clearing method.

                                        ...Jim Thompson 

-- 
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
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