Re: Equality detectors in synchronous designs
From: Nico Coesel (nico_at_puntnl.niks)
Date: 06/14/04
- Next message: Phil Newman: "Re: Payload"
- Previous message: Richard Steiner: "Re: I've dumped Linux and moved to Windows XP."
- In reply to: Opua: "Equality detectors in synchronous designs"
- Next in thread: Opua: "Re: Equality detectors in synchronous designs"
- Reply: Opua: "Re: Equality detectors in synchronous designs"
- Messages sorted by: [ date ] [ thread ]
Date: Mon, 14 Jun 2004 21:28:08 GMT
opua@aol.com (Opua) wrote:
>Looking for an 8-bit equality detector for use with LVC series logic in a high
>speed synchronous design. There are no 74688 devices in this family and if I
>make my own, there are typically 4 levels of gates (look at schematic for the
>688). The prop delays will build up to where the output doesn't change state
>in 1 clock period - a requirement for synchronous state machines. The circuit
>will initially clock at 50MHz, with option to go to 125MHz, hence the LVC
>series logic.
>
>Anyone have any thoughts?
Move to FPGA... I strongly doubt you can get to 125MHz. Even in the
cheaper FPGA's (like the Xilinx Spartan 2 series) 125MHz may be
pushing the limits. If you want to run a circuit consisting of logic
gates at 125MHz, ECL is probably the only way to go.
Anyway, how about using 8 XOR ports and an 8 input or-port?
-- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nl
- Next message: Phil Newman: "Re: Payload"
- Previous message: Richard Steiner: "Re: I've dumped Linux and moved to Windows XP."
- In reply to: Opua: "Equality detectors in synchronous designs"
- Next in thread: Opua: "Re: Equality detectors in synchronous designs"
- Reply: Opua: "Re: Equality detectors in synchronous designs"
- Messages sorted by: [ date ] [ thread ]
Relevant Pages
|
