Re: compressing Xilinx bitstreams

From: John Larkin (jjlarkin_at_highSNIPlandTHIStechPLEASEnology.com)
Date: 06/17/04 

Date: Thu, 17 Jun 2004 16:12:19 -0700

On Thu, 17 Jun 2004 22:14:15 GMT, "John_H" <johnhandwork@mail.com>
wrote:

>First, please be aware that the ACSII .rbt file is 8x the simple .bin file
>size. Check the bitgen options and you'll find the ability to generate the
>straight binary file - 1s and 0s at the bit level, not the ASCII character
>level. Compression beyond that may be what you're looking for, but please -
>start with the binary file.
>

Of course. We have a little utility, vaguely like a linker, that
gobbles up Motorola .s28 files and Xilinx .rbt files and builds a rom
image, all properly squashed into bits. It's cute... it even saves the
beginning of the rbt ASCII header in the rom image for FPGA version
verification. My observation was that the bits themselves include long
runs of 1s or 0s.

I'd like to design a board using a 28-pin eprom (space is at a premium
here) but plan hooks for using a bigger Xilinx chip some day, and then
I'd run out of rom space to store the config bits. So having a
compression scheme would give us the margin to use the small eprom.

Suppose the compressed data were an array of bytes. If the MS bit of a
byte were 0, the remaining 7 bits are to be loaded verbatum; if the MS
bit is a 1, the other 7 bits specify a run of up to 63 1's or 0's.

Something like that; the exact numbers may need tuning. Very easy to
unpack, not hard to encode. I'd have to test some actual config files
to see how good something like this could compress.

John

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