Re: Sydney-X1 FPGA Computer Challenges Commodore, Amiga and Apple

From: John Larkin (jjlarkin_at_highSNIPlandTHIStechPLEASEnology.com)
Date: 07/19/04 

Date: Mon, 19 Jul 2004 12:51:42 -0700

On Mon, 19 Jul 2004 19:31:06 +0100, "John Jardine"
<john@jjdesigns.fsnet.co.uk> wrote:

>
>John Larkin <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in message
>news:oqvnf0lhisia9kkajpaptq103d3283025j@4ax.com...
>> On Mon, 19 Jul 2004 17:24:34 +0100, "John Jardine"
>> <john@jjdesigns.fsnet.co.uk> wrote:
>> >rate.
>> PowerBasic returns the good-old-days of clean, fast programming and
>> direct hardware access. I've run useful megahertz-rate FOR loops on a
>> PC using PB. Direct hardware access is allowed under Win9x, and the
>> Totalio utility opens up all the i/o ports under 2K/XP. We even have a
>> utility that locates PCI cards and drags them down into the real
>> memory space where PB can flog them.
>>
>> I wrote a nice little parallel-port serial-DAC bit-banger in PB, and
>> my customer felt the need to rewrite it in VB.NET. It went from 2
>> files (.bas, .exe) to about 25, ran about 0.05 as fast, needed some
>> extra dll's to access the hardware, and never quite worked right.
>>
>> The PowerBasic people are weird, though, but not as weird as
>> Microsoft.
>
>(I've got a screen 12, 'vectored text' programme somewhere on their site)
>>
>> John
>
>Customers?, pah!, who'd have 'em :-) I genuinely try to encourage 'em to
>make small wanted changes to the kit. Y'know, take a bit of control for
>themselves, save themselves a bit of cash, even shoehorn me out of the loop.
>Doesn't happen, They'll religously play the game. Have come to realise that
>(quite sensibly) having paid for a specialist supplier they've no interest
>in doing any of it for themselves.
>The old '486 I use for hardware test was used to run an impedance analyser
>design. DUT Phase shifts measured by a PB machine code loop counter. The
>loops were running at an amazing 10MHz! (Yet again final precision massively
>limited by the ISA bus)
>Wonder what the new PCs are capable of running at?.
>regards
>john
>

My klunky old 700 MHz Dell runs an empty long-integer FOR loop in 35
ns, about 28 MHz. Adding a long-integer increment inside the loop adds
only 3 ns, which may be the consequence of CPU pipelining or
something. A function/sub call adds about 150 ns of overhead, which is
why I prefer GOTO programming.

ISAbus INP takes 1.4 usec!

John

Relevant Pages

  • Re: For loop synthesis and repeated structures, any examples?
    ... I meant that the for loop IS an innefficient constuct ... in the sense that it would paralellise the hardware... ... has almost nothing to do with that design compromise. ... the multiplier, and capturing its output into the right ...
    (comp.lang.verilog)
  • Re: The revelation of St. f0dder the Divine
    ... here is the Gospel according to f0dder.". ... trying to get away with regurgitating f0dder over the application of an old hardware failsafe procedure, I guess you have defaulted on your claim that signal state APIs have any perforance advantages over a polling loop. ... As was pointed out to you Sleep uses WaitForSingleObject as well so any hardware that has problems with it will have the same problem with Sleep. ... waitable objects cause problems ont he K6-2. ...
    (alt.lang.asm)
  • Re: Best main loop ?
    ... I think it is NOT a good idea to run your game ... loop at the maximum speed the hardware will allow. ... Windows processing loop. ... Dolphin does not have a #performDeferred message. ...
    (comp.lang.smalltalk.dolphin)
  • Re: The revelation of St. f0dder the Divine
    ... The polling loop is because... ... This doesn't sound like it would be hardware-specific either, but the old deviant hardware in question was *around* the time of the "too fast" loop instruction. ... [in the unlikely event that I both boot Windows and run Masm:)] ...
    (alt.lang.asm)
  • Re: For loop synthesis and repeated structures, any examples?
    ... loop in synthesis and hardware as compared to equivalent counter ... According to The verilog golden reference guide, the for loop ... output reg F, ... controllled by a clock edge and which does not repeat structures, ...
    (comp.lang.verilog)