Re: Solid State Relays and EMI
From: Arie de Muynck (Sorry_I_hate_spam_at_nomail.com)
Date: 07/27/04
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Date: Tue, 27 Jul 2004 20:12:57 +0200
"David Harper" ...
> "Arie de Muynck" ...
>
> > Did you alrady do the test with the 1nF between driver size and output
side?
>
> Which pins are you suggesting I apply it across? Input ground to output
ground?
Yes. The basic idea is to minimize the RF voltage occurring across the
isolation barrier by shorting it with the cap.
Input GND to output GND is best, to other points it might cause other EMC
problems.
It _may_ help to also put a ceramic 1nF cap across the output. This lowers
the RF voltage across the FETs, half of which would be present at the output
side of the isolation barrier. But it will decrease the output impedance,
so it's a second choice solution only.
Regards,
Arie de Muynck
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