Re: PCB Design

From: John Larkin (jjlarkin_at_highSNIPlandTHIStechPLEASEnology.com)
Date: 08/09/04 

Date: Mon, 09 Aug 2004 10:23:49 -0700

On Mon, 9 Aug 2004 17:46:54 +0100, John Woodgate
<jmw@jmwa.demon.contraspam.yuk> wrote:

>I read in sci.electronics.design that colin
><no.spam.for.me@ntlworld.com> wrote (in <xjNRc.178$YY4.175@newsfe3-gui.n
>tli.net>) about 'PCB Design', on Mon, 9 Aug 2004:
>
>>ive never experienced this resonance,
>
>Then you have been lucky! Set up a nice fat foil-type 1 uF capacitor
>with wire ends in series with a low-value resistor and feed the
>combination from an r.f. generator. Put a scope across the resistor. You
>will see the current peak up at some frequency where the capacitor
>resonates with the inductance of its lead wires and its internal
>inductance, probably below 1 MHz. Then try with 0.1 uF and 0.01 uF. For
>smaller values, you need a different set-up. But it's not difficult to
>find the series resonance of capacitors up to 1 GHz or so.
>
>The resonance is your friend, of course. The capacitor is a super-
>decoupler at the resonance frequency - the only impedance left is the
>ESR. It's what happens to the impedance above that frequency that can
>cause trouble.
>
>The problem with multiple capacitors in parallel is that above the
>frequency where the largest capacitor(usually) resonates, it's inductive
>and can now form a *parallel* resonance with the other caps. This is
>really bad news, because the impedance can peak up to tens of ohms quite
>easily and 100+ ohms isn't ruled out.

Which means that lots of bypass caps are inevitably going to cause
trouble. That's what the oft-published parallel-cap Spice analysies
all show. Funny that it doesn't happen that way in real life.

John

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