Re: PCB Design

From: Ray Anderson (reanderson_at_sbcglobal.net)
Date: 08/12/04 

Date: Thu, 12 Aug 2004 04:28:49 GMT

>>What is this "sun" paper ?
>>
>
>
> Google something like Larry Smith Decoupling CMOS Sun or things
> like that. I can no longer find his classic 1999 paper, the one full
> of Spice silliness. Lately he seems to have discovered planes.
>
> Check out Xilinx's XAPP623 for a hoot.
>
> John
>

The "Sun" papers related to power distribution network design can be
found at http://www.si-list.org/files/published/sun/sun_papers.html .

Larry and I (and a couple others) have been working on the problem of
properly decoupling systems for quite a few years. (I have just left Sun
after 11 years). Regarding the comment that he seems to have discovered
planes lately, I assure you that he has been quite aware of them for a
good long while. The one paper you mention (the 1998 EPEP paper by Smith
and Prymak) mainly deals with the ESL and ESR of ceramic decaps. Several
of the other published papers fully discuss the contribution of the
power planes to the PDN design problem.

In a nutshell I think you will find the following:

PCB level decoupling is only effective for signal integrity purpose up
to the package resonance frequency (typically 80 to 130 MHz for many
ASICS and CPUs). Above that frequency the quality of th epower (Vdd) at
the silicon depends primarily on package level and die level decoupling.
  PCB level decoupling above the package resonance frequency can be
important from a EMI/EMC perspective as high Z peaks in the impedance
profile can cause excessive radiation from the PCB if excited.

There are many different decoupling philosophies as has been mentioned
in this thread. The one that the SI staff at Sun espouses depends on the
use of several (typically 3 values per decade) decap values selected
such that the composite impedance profile is at or below a specified
target impedance. The antiresonance phenomena that people alway talk
about is the result of the interplane capacitance of the PCB resonating
with the parallel inductances of the decaps. By using closely spaced
planes, the level of the ani-resonance peake can be held reasonable
levels. (closely spaced planes exhibit lower values of spreading
inductance).

You'll find a paper published by the Sun group that describes a plane
model composed of orthoganal transmission lines. This model has been
validated in the lab to be accurate up to several GHz. At frequencies
below the package resonance frequency you will find that the inclusion
of the plane model is not terribly important and that you can arrive at
fairly accurate simulations with a 'single node' analysis of the PDN.
Decap placement below the package resonant frequency isn't terribly
positiopn dependent as long as the decaps are placed within about .1
lambda (at the SRF) of the current consumer. (it is a charge time of
flight issue).

Be aware that if you use ultra low ESR decaps you had best use low
inductance mopunting techniques (good mounting pad geometries including
escapes and via placement) as well as closely spaced planes to achieve
low spreading inductance. Failure to use low inductance mounting
techniques will cause excessively high antiresonant peaks and decrease
the effectiveness of the decaps.

The techniques that I've just barely outlined (and the subject of many
of the Sun papers) have been successfully used to decouple many
workstation and servers some of which exhibit target impedances in the
sub-milliohm range.

-Ray Anderson

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