Re: Any good ideas on this circuit problem?

From: Klaus Vestergaard Kragelund (klauskvik_at_hotmail.com)
Date: 09/12/04 

Date: Sun, 12 Sep 2004 11:32:57 +0200

"Winfield Hill" <Winfield_member@newsguy.com> wrote in message
news:chsc5b0331@drn.newsguy.com...
> Tony Williams wrote...
> >
> > Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:
> >
> >> I have this circuit that I'm more or less stuck with. I have an
> >> solution that is working, but I would like to tweek it a bit to
> >> get better performance.
> >
> >> www.microdesign.dk/sed_q_circuit.pdf
> >
> >> The circuit functions fine, but there is too much delay on the
> >> final inverter due to the RC combination of the first resistor
> >> and the parasitic capacitance of the final inverter and the PCB
> >> layout. For the values shown the delay is approximately 250ns
> >> (5k times 50pF).
> >
> > Would it be worth looking at changing this....
> >
> > 23v
> > _| _
> > | \ R27 | \
> > Osc | >o----/\/\---+---| >o
> > |_/ 10k | |_/
> > | /
> > 8v5ref \R28
> > /
> > |___339output
> >
> > To this........
> > 23v
> > |
> > /
> > 23v \R27 (3k3?)
> > _| / _
> > | \ D1 | | \
> > Osc | >o-----|<|---+---| >o
> > |_/ | |_/
> > | /
> > 8v5ref \R28 (1k8?)
> > /
> > |___339output
>
>
> What's wrong with just adding a cap (experiment to find the
> optimum small value), like this,
>
> . 23v 10pF
> . _| ,--||--, _
> . | \ | | | \
> . Osc | >o--+-/\/\-+--+---| >o
> . |_/ R27 | |_/
> . | /
> . 8v5ref \R28
> . /
> . |___339output
>
>
> --

Also what I had in mind in my first troubleshooting. I was however conserned
about the case when the 139 is active - pulling R28 down. Then I think a
negative pulse at the osc output inverter would source a spike of current
into the second gate perhaps leading to SCR latchup. Am I mistaken?

Thanks

Klaus