Re: measuring Vgs(off)

From: Tony Williams (tonyw_at_ledelec.demon.co.uk)
Date: 09/23/04 

Date: Thu, 23 Sep 2004 10:10:32 +0100

In article <knv0l0plqfovic8m7sg8q5ko7jq9uk2605@4ax.com>,
   Paul Burridge <pb@notthisbit.osiris1.co.uk> wrote:

> Yes, I'd expected someone to point out that the "negligible
> current" point was the likely problem area. I can't honestly say
> that I have, because my DVM drops out at 0.01mA! However, in the
> context of the wide spread of parameters one encounters with
> FETs., I'm pretty confident my 'drop-out' zone for current
> measurement is not too far off the mark. But you've answered my
> question and as ever I'm grateful to you for that. I actually
> found it more difficult measuring Id as Vgs approached zero.
[snip]

 Paul, you might try the belt 'n braces method.

                  --+--+15v
                    |
                 |--+
            +--->|
            | |--+
            | |
            | +------->To DVM
            | |
            | \
            | /R
            | \
            | |
        0v--+-------+------->

 Self-bias the jfet with resistor R, and measure the
 voltage across it. This gives you the Vgs and Id.

 Use two values of R, say 1k and 5k, and plug the
 results into the Id = Idss(etc) equation. Solve the
 two equations for Idss and Vgs(off).

 You've been wandering around this problem for days now.
 It might help if you could get hold of an old Siliconix
 Technical Article, TA70-2, first published in Electronics
 Design in May 1970, then included in the App Notes at the
 rear of most Siliconix FET data books for the next 15 or
 20 years thereafter.

 TA70-2 shows you how to plot Id/Vgs and gfs/Vgs curves
 and use them to determine the best bias point for minimum
 Id and gfs variations. 

-- 
Tony Williams.