Re: Timer circuit help

From: John Fields (jfields_at_austininstruments.com)
Date: 11/21/04 

Date: Sun, 21 Nov 2004 13:03:13 -0600

On Sun, 21 Nov 2004 17:12:09 +0000 (UTC), kensmith@green.rahul.net
(Ken Smith) wrote:

>In article <bo91q09lh5av2buu86oh6ca7oj09rcpnc2@4ax.com>,
>John Fields <jfields@austininstruments.com> wrote:
>>On Sun, 21 Nov 2004 01:49:02 +0000 (UTC), kensmith@green.rahul.net
>>(Ken Smith) wrote:
>>
>>>In article <5tqvp0hdt2ppkh3infht66i7pe2mlhk64l@4ax.com>,
>>>John Fields <jfields@austininstruments.com> wrote:
>[...]
>>> -----!\
>>> ----+ ! O--+------------------------!\
>>> -----!/ ! ! O----- Out
>>> ! Qn -----!/
>>> !
>>> ! --------------------
>>> -----!R 4060 !
>>> ! !
>>> ----!--!>o- !
>>> ! ! ! !
>>> ! --------------------
>>> ! !
>>> ! ---
>>> ! ---
>>> ! !
>>> +---/\/\/\--+
>>> ! !
>>> ! \
>>> ! /
>>> ! \
>>> ! !
>>> ! /!-----
>>> ----O !
>>> \!--------Q(n+2)
>>
>>---
>>Neat, _and_ 50% duty cycle, but since the earliest output from the
>>4060 is Q3, there will be 8 clock cycles between IN going high and OUT
>>going active, which isn't what the OP's timing diagram:
>
>
>No, the circuit works fine. Those are all NOR gates.
>
>When the reset first goes away, Qn is low. The output goes high right
>away.
>
>After some clock cycles, Qn goes high causing the low on the output.
>
>After that same number of pulses, Qn goes low. 

---
Yes, I see it now. Very nice!
Thanks,
-- 
John Fields

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