DDR SDRAM with Xilinx Virtex 2 on self designed PCB

From: Elmo (ikeepthespiritalive_at_freenet.de)
Date: 11/22/04 

Date: Mon, 22 Nov 2004 13:08:51 +0100

Hello,

last week I started the development and design of a PCB with an FPGA (Xilinx
Virtex 2) and two DDR-SDRAMs in parallel. No big deal, I thought, keeping in
mind the most obvious design rules, i.e. combining the adress lines and
separating the data and strobe (DQS) lines. But now I came across the many
other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE,
etc. My first idea was to also combine them for both modules. Lately I
wondered if I am right with that assumption?

Regards, Elmo

Relevant Pages

  • DDR SDRAM with Xilinx Virtex 2 on self designed PCB
    ... last week I started the development and design of a PCB with an FPGA (Xilinx ... Virtex 2) and two DDR-SDRAMs in parallel. ... other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, ...
    (sci.electronics.cad)
  • DDR SDRAM with Xilinx Virtex 2 on self designed PCB
    ... last week I started the development and design of a PCB with an FPGA (Xilinx ... Virtex 2) and two DDR-SDRAMs in parallel. ... other signals there are, e.g. the clock signals, S0 and S1, CAS, RAS, WE, ...
    (comp.arch.embedded)
  • Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
    ... >last week I started the development and design of a PCB with an FPGA (Xilinx ... >Virtex 2) and two DDR-SDRAMs in parallel. ... to precharge one of the chips while you are performing a ...
    (comp.arch.embedded)
  • Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
    ... >last week I started the development and design of a PCB with an FPGA (Xilinx ... >Virtex 2) and two DDR-SDRAMs in parallel. ... to precharge one of the chips while you are performing a ...
    (sci.electronics.cad)
  • Re: DDR SDRAM with Xilinx Virtex 2 on self designed PCB
    ... >last week I started the development and design of a PCB with an FPGA (Xilinx ... >Virtex 2) and two DDR-SDRAMs in parallel. ... to precharge one of the chips while you are performing a ...
    (sci.electronics.design)