Re: Timer circuit help

From: Terry Pinnell (terrypinDELETE_at_THESEdial.pipex.com)
Date: 11/26/04 

Date: Fri, 26 Nov 2004 08:19:11 +0000

kensmith@green.rahul.net (Ken Smith) wrote:

>In article <bdhcq0h44lamsrsca08gi2hmn4s9poaf6e@4ax.com>,
>Terry Pinnell <terrypinDELETE@THESEdial.pipex.com> wrote:
>[...]
>
>>Thanks for stepping me through that. But I'm darned if I can get it
>>simulating with CM. I've either slipped up somewhere in the schematic,
>>or neither of CM's tricky 555 models are obliging. I'm packing it in
>>for now. Here's my schematic: spot the mistakes!

I assume you've now seen the error I made. As Fred pointed out so
graciously: "...he has that R5/R3 diode part screwed up, shunting C1
with R3..." I must have gone over that drawing a dozen times, and
still missed that careless slip.
>
>If CM vexes you so, perhaps you should stop using it.

It certainly has its quirks, but taking CM's schematics and Spice
facilities overall, it's excellent - better than most, IMO. (I've
looked at quite a few; see my notes and links to some 60 ECAD programs
at http://www.terrypin.dial.pipex.com/ECADList.html )
Anyway, I certainly wouldn't consider abandoning it just because some
models are reluctant to work!

That said, 555-based circuits do seem the hardest work of all. I
usually have to try:
- different Spice settings (GMIN, RELTOL, ABSTOL, VNTOL, ITL4, etc)
- different time steps
- Gear instead of trapezoidal integration
- adding RShunt
- slapping the monitor
... and still often fail to get a good run! But as it happens, once
I'd corrected my wiring error, Fred's circuit simulated straight off.

>>http://www.terrypin.dial.pipex.com/Images/PulserFB-NOSIM.gif

>IIRC, the VCC of the 555s is also connected to the INPUT in freds version.
>This is haw he ensures the right startup conditions.

Actually, he was inconsistent. In his final correction (with R/10
added at IN), he lost his previous explicit connection to Vcc. Whether
deliberately or a typo, I don't know. But it's of no consequence
anyway. CM now simulates fine, with Vdd connected either permanently
or via IN.

Here's my schematic (hopefully correct now) and a couple of
simulations. (Note that I added the 10 nF caps out of habit; I assume
they are non-critical.)
http://www.terrypin.dial.pipex.com/Images/PulserFB-Flaw1.gif

As you see, a minor flaw in this clever circuit is the usual
inconsistency in a 555 astable's first pulse; about 17% longer than
subsequent ones in my simulation. Irrelevant to the OP, of course.

Arguably more serious, the circuit is intolerant about cap values. It
fails if the difference in values between C1 and C2 is above about
13%.

Notes on simulations
=====================
          uF ms (*)
Run # C1 C2 Pulses 1st Next Notes
----- --- --- ------ --- ---- --------------------------------
 1 1.0 1.0 3 170 147 The usual minor 555 astable flaw
 2 1.1 1.0 3 189 160 Ditto
 3 1.14 1.0 2 204 - Only 1 *short* pulse
 4 1.0 0.88 2 172 - Ditto
 
 (*) Pulse period target = ~ 170 ms, i.e 6 Hz

I'm not sure if it can be adapted to deliver 4 pulses instead of 3? 

-- 
Terry Pinnell
Hobbyist, West Sussex, UK
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