Re: RANT - Buying online from Maxims Website From Hell

From: Ben Bradley (ben_nospam_bradley_at_mindspring.com)
Date: 11/28/04 

Date: Sun, 28 Nov 2004 05:36:13 GMT

On Wed, 24 Nov 2004 15:07:02 GMT, Bob Stephens
<stephensyomamadigital@earthlink.net> wrote:

>On Wed, 24 Nov 2004 02:36:34 -0000, john jardine wrote:

>> Yes. Couple of week ago, to pursue an idea, I tried to buy 2 of the newish
>> AD9833 DDS chips. After much buggering about, seemed best solution was to

>> ...

>BTW I stumbled on someting they don't mention in the data ***.
>
>They claim that "...NCOs inherently generate continuous phase signals, thus
>avoiding any output discontinuity when switching between frequencies."
>
>Well, I'm using this chip as a swept sinewave generator, and unless you
>handle it right it's discontinuous as hell. Merely updating the frequency
>register does not update the output synchronously. There is a settling time
>where the output waveform is unstable. The workaround for this is to enable
>frequency register 0 with the starting frequency, preload frequency
>register1 with the next value and flip the frequency0/1 enable bit, load
>the next value into frequency0, toggle the bit etc.

   I'm sure this (load one register while the other is active) is the
way it's intended to be done, and is the very reason it has two
frequency registers, and it's easy to argue that this is a big
omission to not describe doing it that way in the data ***
(ESPECIALLY when an eval board comes with software that does it
wrong). It's been a while since I looked at the data ***, and I've
never even used or seen the actual chip, but ISTR the data/commands
are sent through a serial protocol such as SPI, or something with
clock and data lines. The protocol on these things is always eight
bit, and every time eight bits is transferred, those bits are loaded
into the apropriate bits of the destination register. If it's the
currently operating frequency register, the lower (presuming it loads
the lower first) eight bits will then have the eight LSB's of your new
desired word, where the upper bits will have the original word's bits.
If the new word's upper bits are different, then you're going to have
a short time where the frequency register contains neither the old
frequency, nor the new frequency, and it's going to send out some odd
frequency(ies) until the whole register is updated.
   Go to http://groups.google.com and put in "AD9833 DDS question"
(without the quotes), and you'll see a thread(s) from last March about
this very thing.
   I now recall having a similar situation years earlier, that taught
me about this. About 20+ years ago I put a General Instrument
AY-3-something sound-generator chip (back then it was the common
sound/music chip in arcade game machines) onto an Apple ][ expansion
card and programmed it to generate tones using "poke" commands in
Basic. I got it to do a musical scale by generating the appropriate
numbers and putting them into the chip's divide regisister, which was,
IIRC, 14 bits. Regardless, it took two 8-bit transfers to load it with
the proper bits for a tone. I ran this program (it generated each tone
for about 1/2 second, then went to the next in the scale) for a friend
who worked with game machines, and he said he heard a glitch every
time the pitch changed, and asked why. I said I didn't know, but he
was sure the glitch was there, because he heard these chips in game
machines all the time and they didn't have any glitch when going from
one tone to the next. It wasn't until later that I figured out that
during time between the two pokes (in interpreted BASIC, on a 1 MHZ
6502) only one register had been updated, and the pitch generated was,
for a short but audible time, neither the old nor the new pitch. If I
had written a short assembly routine to load both registers (I see it
now, lda hibyte, ldx lobyte, sta ay_3_freqhi, stx ay_3_freqlo rts),
the whole register would have been updated within such a short time
that no glitch would be heard.

>Bob

-----
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