Re: 528MHz clock level conversion

From: Rene Tschaggelar (none_at_none.net)
Date: 01/05/05 

Date: Wed, 05 Jan 2005 14:24:52 +0100

RobJ wrote:

> Ian wrote:
>
>>I'm surprised you say that about LVDS - I've used FPGA LVDS
>>outputs at 600MHz with no problems. Waveform was very clean,
>>except for about 100psec timing difference between positive and
>>negative transitions.
>>
>
>
> Ian -
>
> What FPGA family has that kind of LVDS output performance? Are you talking
> about 600MHz clock or data outputs? Virtex-2 runs out of gas at around
> 400MHz for LVDS clock outputs (i.e., 800MHz data). I'd be really surprised
> to hear that a Xilinx competitor can do 50% better than that.

Not Ian, nevertheless. There are very fast FPGA families,
such as the Altera Mercury, Altera Stratix, Altera StratixGX,
the last having 3.125 GBit transceivers.

http://www.altera.com/products/devices/stratixgx/sgx-index.jsp

The point is less in having the fast transceivers, than the
lower gate count.

Rene 

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