Re: How to design this circuit?

From: Mac (foo_at_bar.net)
Date: 01/18/05 

Date: Tue, 18 Jan 2005 04:21:19 GMT

On Mon, 17 Jan 2005 22:38:14 +0000, Tobias Weingartner wrote:

> I'm looking for some way to figure out a circuit that will lock onto
> a signal (0-5v, binary) in such a way that no matter what the current
> frequency of the input signal (ok, within reason, 720 p/s to 21600 p/s),
> the output signal would be 100 times the input frequency.
>
> In other words, I'd like to have 50 equally spaced pulses occur between
> consecutive transitions of the input signal?

I can think of two promising ways to make this work. In general, since the
circuit involves predicting the future, it is impossible to make it work
perfectly.

But, if you know that the pulse repetition rate doesn't change
too much from pulse to pulse, then it might work satisfactorily
in practice. Or if you can tolerate a delay.

Option 1: You can use a digital approach with a CPLD or microcontroller.
The idea would be that you use the last period as an estimate for the
current period, and spit out your output pulses accordingly. In a
microcontroller, you might have to use a PWM or some kind of special
output. In a PLD, you can have a custom counter running much faster than
your maximum input frequency.

If a delay of one pulse is tolerable, you might be able to make
it work really well because then you would know the exact period ahead of
time.

Option 2: Use a phase lock loop (PLL) where the VCO output is divided down
by 100 prior to being fed into the reference input. It might be a
challenge to make a PLL stay locked over this frequency range. I don't
know that much about PLL's. You might have to do it all at a higher
frequency, then mix down prior to the final output.

If you go with option 1, a DDS or NCO could possibly be used. It
might be pretty easy to build the NCO into a CPLD.

If I had to prototype this quickly, I would probably try to put the
whole thing into a CPLD.

HTH!

--Mac

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