Re: Scope Trigger for digital scope

From: Nico Coesel (nico_at_puntnl.niks)
Date: 02/02/05 

Date: Wed, 02 Feb 2005 08:28:31 GMT

mike <spamme0@netscape.net> wrote:

>dlharmon wrote:
>> The ADC will be running continuously with the data being stored to
>> SDRAM (circular buffer). The problem with software triggering is the
>> aliasing of signals over 40MHz. I plan to use equivalent time
>> sampling. I should have noted that in the original post. I need the
>> trigger data so I can know where to put each data point on the screen,
>> and 12.5ns is not precise enough. For instance, what I need to know is
>> that the trigger occurred 3.4ns before the 12345678th clock cycle of
>> the ADC. This is one of those problems I see no digital solution to.
>>
>> I realize the limitations of undersampling/equivalent time sampling,
>> and most of them will not matter for this particular application.
>>
>> Tek has some info on equivalent time sampling here:
>> http://www.tek.com/Measurement/App_Notes/RTvET/ap-RTvET.html
>>
>> I will be publishing this design on my website once it is built and
>> working.
>>
>
>Equivalent time sampling can be extraordinarily difficult and here are
>some of the reasons why.
>
>Your trigger system bandwidth has to be as high as the equivalent time
>frequency response.
>
>You have many more sources of error and jitter. Individual components
>must be a LOT better than the equivalent time resolution multiple to
>stay within the total very much smaller error budget.
>
>Your trigger threshold has to be absolutely independent of the input
>waveform. Small cycle-cycle variations in the input waveform can cause
>catastrophic shifts in the effective trigger threshold even when those
>changes happen far outside the area of interest. This is common when
>looking at digital signals. Fixing this is harder than it sounds.
>
>In the TEK TDS540, they do it this way.
>At the trigger event, start two fast positive ramps and store the
>acquisition memory reference pointer.
>At the next positive clock, start discharging the first ramp at a slower
>rate and time how long it takes to discharge.
>At the next negative clock, start discharging the second ramp at a
>slower rate and time how long it takes to discharge.
>This eliminates all the problems you get when the clock and the trigger
>are almost coincident. You always have at least one good ramp interval.
>But you need two of everything. And you need an absolutely symmetrical
>clock.
>

So they are actually measuring the difference between the clock and
the trigger to determine where the collected samples should go when
displaying the signal? 

-- 
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Relevant Pages

  • Re: Scope Trigger for digital scope
    ... > Tek has some info on equivalent time sampling here: ... Equivalent time sampling can be extraordinarily difficult and here are ... Your trigger system bandwidth has to be as high as the equivalent time ... At the next positive clock, start discharging the first ramp at a slower ...
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  • Re: Scope Trigger for digital scope
    ... >> The ADC will be running continuously with the data being stored to ... >> trigger data so I can know where to put each data point on the screen, ... >Equivalent time sampling can be extraordinarily difficult and here are ... start discharging the first ramp at a slower ...
    (sci.electronics.design)
  • Re: Scope Trigger for digital scope
    ... >>Equivalent time sampling can be extraordinarily difficult and here are ... >>Your trigger system bandwidth has to be as high as the equivalent time ... If you don't need to trigger on faster ...
    (sci.electronics.design)
  • Re: Scope Trigger for digital scope
    ... The ADC will be running continuously with the data being stored to ... trigger data so I can know where to put each data point on the screen, ... I realize the limitations of undersampling/equivalent time sampling, ... Tek has some info on equivalent time sampling here: ...
    (sci.electronics.design)
  • Re: Scope Trigger for digital scope
    ... > signals above 40MHz so I will need some form of trigger. ... > the integrator each clock cycle. ... any suggestions for the trigger comparator? ... delay versus ADC output has to include a 2nsec step when the trigger ...
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