CMOS logic, efficiency versus frequency?

From: John Doe (jdoe_at_usenet.is.the.real.thing.com)
Date: 02/11/05 

Date: Fri, 11 Feb 2005 14:31:28 GMT

In as many words as possible, someone is apparently trying to tell me
that CMOS logic becomes abnormally inefficient as operating frequency
rises, that it's only efficient when idle.

I have designed and built lots of circuits with CMOS logic (thanks to
National Semiconductor's 1988 CMOS logic data book). The family
seemed great for micropower devices including oscillators.

My main question is this:
As operating frequency rises within normal limits, does CMOS become
grossly inefficient compared to other typical forms of logic like
maybe TTL? I don't know much about typical logic families.

>From what I recall, the main CMOS power consumption problem occurs
when inputs rise and fall slowly, that it is extremely low power
during normal operation.

Thank you. 

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  • Re: CMOS logic, efficiency versus frequency?
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  • Re: CMOS logic, efficiency versus frequency?
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  • Re: CMOS logic, efficiency versus frequency?
    ... > that CMOS logic becomes abnormally inefficient as operating frequency ... > rises, that it's only efficient when idle. ... the main CMOS power consumption problem occurs ...
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